IC,Cable Equalizer,LLCC,64PIN,PLASTIC

ADN8102ACPZ

Manufacturer Part NumberADN8102ACPZ
DescriptionIC,Cable Equalizer,LLCC,64PIN,PLASTIC
ManufacturerAnalog Devices Inc
SeriesXStream™
ADN8102ACPZ datasheet
 


Specifications of ADN8102ACPZ

ApplicationsEthernet ControllerInterfaceI²C
Voltage - Supply1.8 V ~ 3.3 VPackage / Case64-LFCSP
Mounting TypeSurface MountLead Free Status / RoHS StatusLead free / RoHS Compliant
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FEATURES
Optimized for dc to 3.75 Gbps data
Programmable input equalization
Up to 22 dB boost at 1.875 GHz
Compensates up to 30 meters of CX4 cable up to 3.75 Gbps
Compensates up to 40 inches of FR4 up to 3.75 Gbps
Programmable output pre-emphasis/de-emphasis
Up to 12 dB boost at 1.875 GHz (3.75 Gbps)
Compensates up to 15 meters of CX4 cable up to 3.75 Gbps
Compensates up to 40 inches of FR4 up to 3.75 Gbps
Flexible 1.8 V to 3.3 V core supply
Per lane P/N pair inversion for routing ease
Low power: 125 mW/channel up to 3.75 Gbps
DC- or ac-coupled differential CML inputs
Programmable CML output levels
50 Ω on-chip termination
Loss-of-signal detection
Temperature range operation: −40°C to +85°C
Supports 8b10b, scrambled, or uncoded NRZ data
2
I
C control interface
64-lead LFCSP (QFN) package
APPLICATIONS
10GBase-CX4
HiGig™
InfiniBand®
1×, 2× Fibre Channel
XAUI™
Gigabit Ethernet over backplane or cable
CPRI™
50 Ω cables
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
3.75 Gbps Quad Bidirectional
CX4 Eq ualizer
FUNCTIONAL BLOCK DIAGRAM
LOS_B
ADN8102
RECEIVE
EQUALIZATION
PRE-EMPHASIS
Ix_B[3:0]
EQ
2:1
LB
TRANSMIT
PRE-EMPHASIS
EQUALIZATION
Ox_A[3:0]
PE
2:1
ADDR[1:0]
SCL
SDA
CONTROL LOGIC
RESET
Figure 1.
GENERAL DESCRIPTION
The ADN8102 is a quad, bidirectional, CX4 cable/backplane
equalizer with eight differential PECL-/CML-compatible inputs
with programmable equalization and eight differential CML
outputs with programmable output levels and pre-emphasis or
de-emphasis. The operation of this device is optimized for NRZ
data at rates up to 3.75 Gbps.
The receive inputs provide programmable equalization to
compensate for up to 30 meters of CX4 cable (24 AWG) or
40 inches of FR4, and programmable pre-emphasis to compensate
for up to 15 meters of CX4 cable (24 AWG) or 40 inches of FR4
at 3.75 Gbps. Each channel also provides programmable loss-of-
signal detection and loopback capability for system testing and
debugging.
The ADN8102 is controlled through toggle pins, an I
interface that provides more flexible control, or a combination of
both. Every channel implements an asynchronous path supporting
dc to 3.75 Gbps NRZ data, fully independent of other channels. The
ADN8102 has low latency and very low channel-to-channel skew.
The main application for the ADN8102 is to support switching
in chassis-to-chassis applications over CX4 or InfiniBand cables.
The ADN8102 is packaged in a 9 mm × 9 mm 64-lead LFCSP
(QFN) package and operates from −40°C to +85°C.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2008–2010 Analog Devices, Inc. All rights reserved.
ADN8102
TRANSMIT
Ox_B[3:0]
PE
LOS_A
RECEIVE
EQ
Ix_A[3:0]
EQ_A[1:0]
PE_A[1:0]
EQ_B[1:0]
PE_B[1:0]
ENA
ENB
2
C® control
www.analog.com

ADN8102ACPZ Summary of contents

  • Page 1

    FEATURES Optimized for dc to 3.75 Gbps data Programmable input equalization boost at 1.875 GHz Compensates meters of CX4 cable up to 3.75 Gbps Compensates inches of FR4 up to ...

  • Page 2

    ADN8102 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications ..................................................................................... 3 Timing Specifications .................................................................. 5 Absolute Maximum Ratings ............................................................ 6 ESD Caution .................................................................................. 6 Pin ...

  • Page 3

    SPECIFICATIONS TTI TTO 25°C, unless otherwise noted. A Table 1. Parameter DYNAMIC PERFORMANCE Maximum Data Rate/Channel (NRZ) Deterministic Jitter Random Jitter Residual ...

  • Page 4

    ADN8102 Parameter Output Voltage Range Output Current Output Resistance Output Return Loss LOS CHARACTERISTICS Assert Level Deassert Level POWER SUPPLY Operating Range TTI V TTO Supply Current I TTO I CC LOGIC CHARACTERISTICS Input High, ...

  • Page 5

    TIMING SPECIFICATIONS 2 Table Timing Parameters Parameter Min Max f 0 400 SCL t 0.6 Not applicable HD:STA t 0.6 Not applicable SU:STA t 1.3 Not applicable LOW t 0.6 Not applicable HIGH t 0 Not applicable ...

  • Page 6

    ADN8102 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Rating 3 0.6 V TTI 0.6 V TTO CC Internal Power Dissipation 4.26 W Differential Input Voltage 2.0 V Logic ...

  • Page 7

    PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET LOS_A Table 4. Pin Function Descriptions Pin No. Mnemonic Type 1 RESET Control 2 LOS_A Digital I/O 3 IN_A0 I/O 4 IP_A0 I/O 5 VCC Power 6 IN_A1 I/O 7 IP_A1 I/O 8 VTTI ...

  • Page 8

    ADN8102 Pin No. Mnemonic Type 28 ON_B3 I/O 29 OP_B3 I/O 30 ENB Control 31 PE_B1 Control 32 PE_B0 Control 33 EQ_B0 Control 34 EQ_B1 Control 35 IN_B3 I/O 36 IP_B3 I/O 37 VEE Power 38 IN_B2 I/O 39 IP_B2 ...

  • Page 9

    TYPICAL PERFORMANCE CHARACTERISTICS DATA OUT PATTERN GENERATOR 50ps/DIV Figure 6. 3.25 Gbps Input Eye (TP1 from Figure 5) 50ps/DIV Figure 7. 3.75 Gbps Input Eye (TP1 from Figure 5) 50Ω CABLES 50Ω CABLES INPUT OUTPUT PIN PIN ...

  • Page 10

    ADN8102 DATA OUT PATTERN GENERATOR 50ps/DIV REFERENCE EYE DIAGRAM AT TP1 50ps/DIV Figure 11. 3.25 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 from Figure 10) 50ps/DIV Figure 12. 3.75 Gbps Input Eye, 40 Inch FR4 Input Channel (TP2 ...

  • Page 11

    DATA OUT PATTERN GENERATOR 50ps/DIV REFERENCE EYE DIAGRAM AT TP1 50ps/DIV Figure 16. 3.25 Gbps Input Eye, 30 Meters CX4 Cable (TP2 from Figure 15) 50ps/DIV Figure 17. 3.75 Gbps Input Eye, 30 Meters CX4 Cable (TP2 from Figure 15) ...

  • Page 12

    ADN8102 DATA OUT PATTERN GENERATOR 50ps/DIV REFERENCE EYE DIAGRAM AT TP1 50ps/DIV Figure 21. 3.25 Gbps Output Eye, 40 Inch FR4 Output Channel (TP3 from Figure 20) 50ps/DIV Figure 22. 3.75 Gbps Output Eye, 40 Inch FR4 ...

  • Page 13

    DATA OUT PATTERN GENERATOR 50ps/DIV REFERENCE EYE DIAGRAM AT TP1 50ps/DIV Figure 26. 3.25 Gbps Output Eye, 15 Meters CX4 Cable (TP3 from Figure 25) 50ps/DIV Figure 27. 3.75 Gbps Output Eye, 15 Meters CX4 Cable, PE ...

  • Page 14

    ADN8102 DATA RATE (Hz) Figure 30. Deterministic Jitter vs. Data Rate 100 0.5 1.0 1.5 DIFFERENTIAL INPUT SWING ...

  • Page 15

    JITTER (ps) Figure 36. Random Jitter Histogram 100 –60 Figure 37. Rise Time (t Rev. ...

  • Page 16

    ADN8102 THEORY OF OPERATION INTRODUCTION The ADN8102 is a quad, bidirectional cable and backplane equalizer that provides both input equalization and output pre- emphasis on both the line card and cable sides of the device. The device supports full loopback ...

  • Page 17

    RECEIVERS Input Structure and Input Levels The ADN8102 receiver inputs incorporate 50 Ω termination resistors, ESD protection, and a multizero transfer function equalizer that can be optimized for backplane or cable operation. Each channel also provides a programmable LOS function ...

  • Page 18

    ADN8102 Table 8. Receive Equalizer Boost vs. Setting (CX4 and FR4 Optimized Maps) IN_Ax/IN_Bx EQ_A[1:0] and Configuration, EQ_B[1:0] Pins EQ[2: Don’t care Table ...

  • Page 19

    Table 10. LOS Threshold and Hysteresis Control Registers Name Address Bit 7 Bit 6 IN_A/IN_B 0x81, THRESH[6] LOS threshold 0xA1 IN_A/IN_B 0x82, HYST[6] LOS hysteresis 0xA2 Table 11. LOS Status Registers Name Address Bit 7 IN_A/IN_B 0x1F, STICKY LOS status ...

  • Page 20

    ADN8102 LOOPBACK The ADN8102 provides loopback on both input ports (Port A: cable interface input, and Port B: line card interface input). The external loopback toggle pin, LB, controls the loopback of the Port B input only (board side loopback). ...

  • Page 21

    TRANSMITTERS Output Structure and Output Levels The ADN8102 transmitter outputs incorporate 50 Ω termina- tion resistors, ESD protection, and an output current switch. Each port provides control of both the absolute output level and the pre-emphasis output level. It should ...

  • Page 22

    ADN8102 Table 17. Output Level Settings V (mV) V (mV) V (mV) SW-DC SW-PE DPP- 100 50 150 100 50 250 100 50 350 100 50 450 100 50 550 100 50 650 100 100 100 200 100 ...

  • Page 23

    V (mV) V (mV) V (mV) SW-DC SW-PE DPP-DC 450 450 900 450 550 900 450 650 900 450 750 900 450 850 900 450 950 900 450 1050 900 500 500 1000 500 600 1000 500 700 1000 500 ...

  • Page 24

    ADN8102 SELECTIVE SQUELCH AND DISABLE Each transmitter is equipped with output disable and output squelch controls. Disable is a full power-down state: the trans- mitter current is reduced to zero, and the output pins pull but ...

  • Page 25

    I C CONTROL INTERFACE SERIAL INTERFACE GENERAL FUNCTIONALITY The ADN8102 register set is controlled through a 2-wire interface. The ADN8102 acts only Therefore, the I C bus in the system needs to ...

  • Page 26

    ADN8102 INTERFACE DATA TRANSFERS—DATA READ To read data from the ADN8102 register set, a microcontroller any other I C master, needs to send the appropriate control signals to the ADN8102 slave device. The steps that ...

  • Page 27

    APPLICATIONS INFORMATION OUTPUT COMPLIANCE In low voltage applications, users must pay careful attention to both the differential and common-mode signal levels. The choice of output voltage swing, preemphasis setting, supply voltages (V and V ), and output coupling (ac or ...

  • Page 28

    ADN8102 Table 21. Output Compliance for AC-Coupled Outputs V (mV) V (mV) PE (dB) I SW-DC SW-PE 200 200 0.00 8 200 300 3.52 12 200 400 6.02 16 200 500 7.96 20 200 600 9.54 24 200 700 10.88 ...

  • Page 29

    PRINTED CIRCUIT BOARD (PCB) LAYOUT GUIDELINES The high speed differential inputs and outputs should be routed with 100 Ω controlled impedance, differential transmission lines. The transmission lines, either microstrip or stripline, should be referenced to a solid low impedance reference ...

  • Page 30

    ADN8102 Stencil Design for the Thermal Paddle To effectively remove heat from the package and to enhance electrical performance, the thermal paddle must be soldered (bonded) to the PCB thermal paddle, preferably with minimum voids. However, eliminating voids may not ...

  • Page 31

    REGISTER MAP 2 Table 22 Register Definitions Name Address Bit 7 Bit 6 Reset 0x00 Loopback 0x02 control Control 0x0F interface mode TxHeadroom 0x23 TxH_B3 TxH_B2 IN_A 0x80 PNSWAP configuration IN_A LOS 0x81 THRESH[6] threshold IN_A LOS 0x82 ...

  • Page 32

    ADN8102 Name Address Bit 7 Bit 6 OUT_A 0xC0 configuration OUT_A 0xC1 PE CTL Output Level SRC Control 1 0xC2 OUT_A Output Level Control 0 OUT_A 0xC3 squelch control OUT_B 0xE0 configuration OUT_B 0xE1 PE CTL Output Level SRC Control ...

  • Page 33

    ... BSC SQ PIN 1 INDICATOR 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE Model 1 Temperature Range ADN8102ACPZ −40°C to +85°C ADN8102ACPZ-R7 −40°C to +85°C ADN8102-EVALZ RoHS Compliant Part. 9.00 0.60 MAX 0.60 MAX 49 48 8.75 TOP BSC SQ VIEW 0.50 0.40 ...

  • Page 34

    ADN8102 NOTES Rev Page ...

  • Page 35

    NOTES Rev Page ADN8102 ...

  • Page 36

    ADN8102 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2008–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07060-0-10/10(B) Rev ...