ADN8102ACPZ Analog Devices Inc, ADN8102ACPZ Datasheet - Page 16

• Manufacturer Part Number: ADN8102ACPZ
• Description: IC,Cable Equalizer,LLCC,64PIN,PLASTIC
• Manufacturer: Analog Devices Inc
• Series: XStream™r

Specifications of ADN8102ACPZ

• Applications: Ethernet Controller
• Interface: I²C
• Voltage - Supply: 1.8 V ~ 3.3 V
• Package / Case: 64-LFCSP
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADN8102
THEORY OF OPERATION
INTRODUCTION
The ADN8102 is a quad, bidirectional cable and backplane
equalizer that provides both input equalization and output pre-
emphasis on both the line card and cable sides of the device.
The device supports full loopback and through connectivity
of the two unidirectional half-links, each consisting of four
differential signal pairs.
The ADN8102 offers extensively programmable output levels
and pre-emphasis as well as the ability to disable the output
current. The receivers integrate a programmable, multizero
equalizer transfer function that is optimized to compensate
either typical backplane or typical cable losses.
The I/O on-chip termination resistors are terminated to user-
settable supplies to support dc coupling in a wide range of logic
styles. The ADN8102 supports a wide core supply range; V
can be set from 1.8 V to 3.3 V. These features, together with
programmable output levels, allow for a wide range of dc- and
ac-coupled I/O configurations.
The ADN8102 supports several control and configuration
modes, as shown in Table 5. The pin control mode offers access
to a subset of the total feature list but allows for a much
simplified control scheme. The primary advantage of using the
serial control interface is that it allows finer resolution in setting
receive equalization, transmitter preemphasis, loss-of-signal
(LOS) behavior, and output levels.
By default, the ADN8102 starts in pin control mode. Strobing
the RESET pin sets all on-chip registers to their default values
and uses pins to configure loopback, PE, and EQ levels. In
Table 5. Control Interface Mode Register
Address
0x0F
Default
0x00
Control
interface mode
Register Name
Bit
7:2
1:0
Bit Name
Reserved
MODE[1:0]
CC
Rev. B | Page 16 of 36
Functionality Description
Set to 0.
00 = toggle pin control. Asynchronous control through toggle pins only.
01 = Loopback control via toggle pins, equalization, and preemphasis via
register-based control through the I
10 = Equalization and preemphasis via toggle pins and loopback control
via register-based control through the I
11 = serial control. Register-based control through the I
mixed mode, loopback is still controlled through the external
pin. The user can override PE and EQ settings in mixed mode.
In serial mode, all functions are accessed through registers, and
the control pin inputs are ignored, except RESET .
The ADN8102 register set is controlled through a 2-wire, I
interface. The ADN8102 acts only as an I
slave address for the ADN8102 I
value b10010 for the upper four bits. The lower two bits are
controlled by the input pins, ADDR[1:0]
ADDR[1:0]
Ox_A[3:0]
Ix_B[3:0]
LOS_B
RESET
SDA
SCL
LB
PRE-EMPHASIS
EQUALIZATION
Figure 38. Simplified Functional Block Diagram
TRANSMIT
RECEIVE
EQ
PE
CONTROL LOGIC
2
2:1
C serial interface.
ADN8102
2
C serial interface.
2
C interface contains the static
2:1
PRE-EMPHASIS
EQUALIZATION
2
TRANSMIT
C slave device. The 7-bit
RECEIVE
PE
EQ
2
C serial interface.
Ox_B[3:0]
LOS_A
Ix_A[3:0]
EQ_A[1:0]
PE_A[1:0]
EQ_B[1:0]
PE_B[1:0]
ENA
ENB
2
C