MT46V64M16P-6T:A Micron Technology Inc, MT46V64M16P-6T:A Datasheet - Page 61

• Manufacturer Part Number: MT46V64M16P-6T:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V64M16P-6T:A

• Density: 1 Gb
• Maximum Clock Rate: 333 MHz
• Package: 66TSOP
• Operating Supply Voltage: 2.5 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Package / Case: 66-TSOP
• Organization: 64Mx16
• Address Bus: 16b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 275mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 33:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
x4, x8 Data Output Timing –
Notes:
DQ (first data no longer valid)
DQ (first data no longer valid)
1.
2.
3. DQ transitioning after DQS transition define the
4. For a x4, only two DQ apply.
5.
6. The data valid window is derived for each DQS transitions and is defined as
All DQ and DQS collectively
t
t
transition, and ends with the last valid DQ transition.
T2n are an “early DQS”; at T3, a “nominal DQS”; and at T3n, a “late DQS”.
t
HP is the lesser of
DQSQ is derived at each DQS clock edge, is not cumulative over time, begins with DQS
QH is derived from
DQ (last data valid)
DQ (last data valid)
DQS
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
DQ 4
CK#
CK
Earliest signal transition
3
6
Latest signal transition
T1
t
t
DQSQ,
CL or
t
HP:
t HP 1
t
t
QH =
CH clock transition collectively when a bank is active.
t
61
QH, and Data Valid Window
t
HP -
t HP 1
t DQSQ 2
t QH 5
t
QHS.
T2
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window
Data
valid
T2
T2
T2
t HP 1
T2n
t DQSQ 2
t QH 5
t
DQSQ window. DQS transitions at T2 and
1Gb: x4, x8, x16 DDR SDRAM
window
t HP 1
T2n
T2n
T2n
Data
valid
T3
t DQSQ 2
t QH 5
©2003 Micron Technology, Inc. All rights reserved.
t HP 1
window
Data
valid
T3
T3
T3
T3n
t DQSQ 2
t QH 5
t HP 1
Operations
t
QH -
T4
window
T3n
T3n
Data
valid
T3n
t
DQSQ.