MT46V64M16P-6T:A Micron Technology Inc, MT46V64M16P-6T:A Datasheet - Page 80

• Manufacturer Part Number: MT46V64M16P-6T:A
• Description: DRAM Chip DDR SDRAM 1G-Bit 64Mx16 2.5V 66-Pin TSOP Tray
• Manufacturer: Micron Technology Inc
• Type: DDR SDRAMr

Specifications of MT46V64M16P-6T:A

• Density: 1 Gb
• Maximum Clock Rate: 333 MHz
• Package: 66TSOP
• Operating Supply Voltage: 2.5 V
• Maximum Random Access Time: 0.7 ns
• Operating Temperature: 0 to 70 °C
• Format - Memory: RAM
• Memory Type: DDR SDRAM
• Memory Size: 1G (64M x 16)
• Speed: 6ns
• Interface: Parallel
• Voltage - Supply: 2.3 V ~ 2.7 V
• Package / Case: 66-TSOP
• Organization: 64Mx16
• Address Bus: 16b
• Access Time (max): 700ps
• Operating Supply Voltage (typ): 2.5V
• Package Type: TSOP
• Operating Temp Range: 0C to 70C
• Operating Supply Voltage (max): 2.7V
• Operating Supply Voltage (min): 2.3V
• Supply Current: 275mA
• Pin Count: 66
• Mounting: Surface Mount
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 52:
PDF: 09005aef80a2f898/Source: 09005aef82a95a3a
DDR_x4x8x16_Core2.fm - 1Gb DDR: Rev. I, Core DDR: Rev. B 12/07 EN
Command 2
Address
DQS
CK#
CK 1
CKE
DM
DQ
t RP 4
t IS
t IS
NOP
T0
Self Refresh Mode
Enter self refresh mode 7
t IH
t IH
t CH
Notes:
t CL
t IS
T1 1
AR
the extended mode register) and NOPs for 200 additional clock cycles before applying a
READ. Any command other than a READ can be performed
reset. NOP or DESELECT commands must be issued during the
1. Clock must be stable until after the SELF REFRESH command has been registered. A change
2. NOPs are interchangeable with DESELECT commands.
3. AUTO REFRESH is not required at this point but is highly recommended.
4. Device must be in the all banks idle state prior to entering self refresh mode.
5.
6.
7. As a general rule, any time self refresh mode is exited, the DRAM may not re-enter the self
8. If the clock frequency is changed during self refresh mode, a DLL reset is required upon exit.
9. Once the device is initialized, V
7b.
7a. The DRAM had been in the self refresh mode for a minimum of 200ms prior to exiting.
7c. At least two AUTO REFRESH commands are performed during each
in clock frequency is allowed before Ta0, provided it is within the specified
Regardless, the clock must be stable before exiting self refresh mode—that is, the clock
must be cycling within specifications by Ta0.
t
LECT commands are allowed until Tb1.
t
can be applied.
refresh mode until all rows have been refreshed via the AUTO REFRESH command at the
distributed refresh rate,
anytime after exiting if each of the following conditions is met:
XSNR is required before any non-READ command can be applied; that is only NOP or DESE-
XSRD (200 cycles of a valid clock with CKE = HIGH) is required before any READ command
t
the DRAM remains out of self refresh mode.
XSNR and
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XSRD are not violated.
Ta0 1
Exit self refresh mode 7
t
REFI, or faster. However, the self refresh mode may be re-entered
t CK
80
t IS
REF
NOP
Ta1
must always be powered within specified range.
t XSNR 5
t XSRD 6
Micron Technology, Inc., reserves the right to change products or specifications without notice.
NOP
Ta2
1Gb: x4, x8, x16 DDR SDRAM
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t IS
Valid 3
Valid
Tb1
t IH
t
XSNR (MIN) after the DLL
©2003 Micron Technology, Inc. All rights reserved.
t
XSNR (MIN) time.
Valid
Tb2
Valid
t
REFI interval while
t
Operations
CK limits.
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Don’t Care
Valid
Valid
Tc1