PIC16LF1518-E/SP Microchip Technology, PIC16LF1518-E/SP Datasheet - Page 219

• Manufacturer Part Number: PIC16LF1518-E/SP
• Description: 28-pin, 28KB Flash, 1024B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 1.8V-3.6V 2
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1518-E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 28KB (16K x 14)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16LF151x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

21.6.5
A Repeated Start condition occurs when the RSEN bit
of the SSPCON2 register is programmed high and the
Master state machine is no longer active. When the
RSEN bit is set, the SCL pin is asserted low. When the
SCL pin is sampled low, the Baud Rate Generator is
loaded and begins counting. The SDA pin is released
(brought high) for one Baud Rate Generator count
(T
SDA is sampled high, the SCL pin will be deasserted
(brought high). When SCL is sampled high, the Baud
Rate Generator is reloaded and begins counting. SDA
and SCL must be sampled high for one T
action is then followed by assertion of the SDA pin
(SDA = 0) for one T
asserted low. Following this, the RSEN bit of the
FIGURE 21-27:
 2010 Microchip Technology Inc.
BRG
). When the Baud Rate Generator times out, if
I
START CONDITION TIMING
2
C MASTER MODE REPEATED
BRG
REPEAT START CONDITION WAVEFORM
SDA
SCL
while SCL is high. SCL is
Write to SSPCON2
occurs here
SDA = 1,
SCL (no change)
BRG
. This
Preliminary
T
BRG
SDA = 1,
SCL = 1
T
BRG
Repeated Start
SSPCON2 register will be automatically cleared and
the Baud Rate Generator will not be reloaded, leaving
the SDA pin held low. As soon as a Start condition is
detected on the SDA and SCL pins, the S bit of the
SSPSTAT register will be set. The SSPIF bit will not be
set until the Baud Rate Generator has timed out.
Sr
PIC16(L)F1516/7/8/9
Note 1: If RSEN is programmed while any other
T
BRG
2: A bus collision during the Repeated Start
S bit set by hardware
At completion of Start bit,
hardware clears RSEN bit
Write to SSPBUF occurs here
event is in progress, it will not take effect.
condition occurs if:
and sets SSPIF
• SDA is sampled low when SCL
• SCL goes low before SDA is
T
BRG
goes from low-to-high.
asserted low. This may indicate
that another master is attempting to
transmit a data ‘1’.
1st bit
T
BRG
DS41452A-page 219