PIC16LF1518-E/SP Microchip Technology, PIC16LF1518-E/SP Datasheet - Page 70

• Manufacturer Part Number: PIC16LF1518-E/SP
• Description: 28-pin, 28KB Flash, 1024B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 1.8V-3.6V 2
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1518-E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 28KB (16K x 14)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16LF151x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC16(L)F1516/7/8/9
6.3
The Ultra Low-Power Brown-Out Reset (ULPBOR) is
an essential part of the Reset subsystem. Refer to
Figure 6-1
modules.
The ULPBOR is used to monitor the external V
When too low of a voltage is detected, the device is
held in Reset. When this occurs, a register bit (BOR) is
changed to indicate that a BOR Reset has occurred.
The same bit is set for both the BOR and the ULP-
BOR. Refer to
6.3.1
The ULPBOR is controlled by the ULPBOR bit of
Configuration Word 2. When the device is erased, the
ULPBOR module defaults to disabled.
6.3.1.1
The output of the ULPBOR module is a signal indicat-
ing whether or not a Reset is to be asserted. This sig-
nal is to be OR’d together with the Reset signal of the
BOR module to provide the generic BOR signal which
goes to the PCON register and to the power control
block.
6.4
The MCLR is an optional external input that can reset
the device. The MCLR function is controlled by the
MCLRE bit of Configuration Word 1 and the LVP bit of
Configuration Word 2
TABLE 6-2:
6.4.1
When MCLR is enabled and the pin is held low, the
device is held in Reset. The MCLR pin is connected to
V
The device has a noise filter in the MCLR Reset path.
The filter will detect and ignore small pulses.
6.4.2
When MCLR is disabled, the pin functions as a general
purpose input and the internal weak pull-up is under
software control. See
for more information.
DS41452A-page 70
DD
Note:
through an internal weak pull-up.
MCLRE
0
1
x
Ultra Low-Power Brown-out Reset
(ULPBOR)
MCLR
to see how the BOR interacts with other
ENABLING ULPBOR
MCLR ENABLED
A Reset does not drive the MCLR pin low.
MCLR DISABLED
ULPBOR Module Output
Register
MCLR CONFIGURATION
Section 12.6 “PORTE Registers”
(Register
6-2.
LVP
0
0
1
4-2).
Disabled
Enabled
Enabled
MCLR
DD
pin.
Preliminary
6.5
The Watchdog Timer generates a Reset if the firmware
does not issue a CLRWDT instruction within the time-out
period. The TO and PD bits in the STATUS register are
changed to indicate the WDT Reset. See
“Watchdog Timer”
6.6
A RESET instruction will cause a device Reset. The RI
bit in the PCON register will be set to ‘0’. See
for default conditions after a RESET instruction has
occurred.
6.7
The device can reset when the Stack Overflows or
Underflows. The STKOVF or STKUNF bits of the PCON
register indicate the Reset condition. These Resets are
enabled by setting the STVREN bit in Configuration
Word 2.
Reset”
6.8
Upon exit of Programming mode, the device will
behave as if a POR had just occurred.
6.9
The Power-up Timer optionally delays device execution
after a BOR or POR event. This timer is typically used to
allow V
running.
The Power-up Timer is controlled by the PWRTE bit of
Configuration Word 1.
6.10
Upon the release of a POR or BOR, the following must
occur before the device will begin executing:
1.
2.
3.
The total time-out will vary based on oscillator configu-
ration and
Section 5.0 “Oscillator Module (With Fail-Safe
Clock Monitor)”
The Power-up Timer and oscillator start-up timer run
independently of MCLR Reset. If MCLR is kept low long
enough, the Power-up Timer and oscillator start-up
timer will expire. Upon bringing MCLR high, the device
will begin execution immediately (see
is useful for testing purposes or to synchronize more
than one device operating in parallel.
Power-up Timer runs to completion (if enabled).
Oscillator start-up timer runs to completion (if
required for oscillator source).
MCLR must be released (if enabled).
DD
for more information.
Watchdog Timer (WDT) Reset
RESET Instruction
Stack Overflow/Underflow Reset
Programming Mode Exit
Power-Up Timer
Start-up Sequence
See
to stabilize before allowing the device to start
Power-up
Section 3.4.2
for more information.
for more information.
 2010 Microchip Technology Inc.
Timer
“Overflow/Underflow
configuration.
Figure
Section 10.0
6-3). This
Table 6-4
See