PIC16LF1518-E/SP Microchip Technology, PIC16LF1518-E/SP Datasheet - Page 32

• Manufacturer Part Number: PIC16LF1518-E/SP
• Description: 28-pin, 28KB Flash, 1024B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 1.8V-3.6V 2
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16LF1518-E/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Program Memory Size: 28KB (16K x 14)
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Processor Series: PIC16LF151x
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 3-6:
Legend:
C00h
C0Bh
C0Ch
C6Fh
C70h
C7Fh
F8Ch
FEAh
FEBh
FECh
FEDh
FEEh
FEFh
F80h
F8Bh
FE3h
FE4h
FE5h
FE6h
FE7h
FE8h
FE9h
FF0h
FFFh
Unimplemented
Core Registers
Common RAM
Read as ‘0’
BANK 24
(Table
70h – 7Fh)
(Accesses
STATUS_SHAD
PCLATH_SHAD
Unimplemented
Core Registers
WREG_SHAD
FSR0L_SHAD
FSR0H_SHAD
FSR1L_SHAD
FSR1H_SHAD
Common RAM
BSR_SHAD
Read as ‘0’
(Table
70h – 7Fh)
(Accesses
Bank 31
STKPTR
TOSH
TOSL
3-2)
—
= Unimplemented data memory locations, read as ‘0’.
3-2)
PIC16(L)F1518/9 MEMORY MAP (CONTINUED)
C8Ch
CEFh
C80h
C8Bh
CF0h
CFFh
Unimplemented
Core Registers
Common RAM
BANK 25
Read as ‘0’
(Table
70h – 7Fh)
(Accesses
3-2)
D0Ch
D00h
D0Bh
D6Fh
D70h
D7Fh
Unimplemented
Core Registers
Common RAM
BANK 26
Read as ‘0’
(Table
70h – 7Fh)
(Accesses
3-2)
D8Bh
D8Ch
DEFh
DFFh
D80h
DF0h
Unimplemented
Core Registers
Common RAM
BANK 27
Read as ‘0’
70h – 7Fh)
(Table
(Accesses
3-2)
E0Ch
E00h
E0Bh
E6Fh
E70h
E7Fh
Unimplemented
Core Registers
Common RAM
Read as ‘0’
BANK 28
70h – 7Fh)
(Table
(Accesses
3-2)
E8Ch
EEFh
E80h
E8Bh
EF0h
EFFh
Unimplemented
Core Registers
Common RAM
Read as ‘0’
BANK 29
70h – 7Fh)
(Table
(Accesses
3-2)
F0Ch
F00h
F0Bh
F6Fh
F70h
F7Fh
Unimplemented
Core Registers
Common RAM
Read as ‘0’
BANK 30
(Table
70h – 7Fh)
(Accesses
3-2)