PIC24FJ64GA306-I/MR Microchip Technology, PIC24FJ64GA306-I/MR Datasheet - Page 162

• Manufacturer Part Number: PIC24FJ64GA306-I/MR
• Description: 16-bit, 16 MIPS, 64 KB Flash, 8 KB RAM, 53 I/O, LCD, XLP W/Vbat 64 QFN 9x9x0.9mm
• Manufacturer: Microchip Technology

PIC24FJ128GA310 FAMILY
REGISTER 10-1:
DS39996F-page 162
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14-3
bit 2
bit 1
bit 0
Note 1:
R/W-0
DSEN
U-0
—
2:
All register bits are reset only in the case of a POR event outside of Deep Sleep mode.
Unlike all other events, a Deep Sleep BOR event will NOT cause a wake-up from Deep Sleep; this
re-arms POR.
DSEN: Deep Sleep Enable bit
1 = Enters Deep Sleep on execution of PWRSAV #0
0 = Enters normal Sleep on execution of PWRSAV #0
Unimplemented: Read as ‘0’
Reserved: Maintain as ‘0’
DSBOR: Deep Sleep BOR Event bit
1 = The DSBOR was active and a BOR event was detected during Deep Sleep
0 = The DSBOR was not active or was active but did not detect a BOR event during Deep Sleep
RELEASE: I/O Pin State Release bit
1 = Upon waking from Deep Sleep, I/O pins maintain their states previous to Deep Sleep entry
0 = Release I/O pins from their state previous to Deep Sleep entry, and allow their respective TRIS and
LAT bits to control their states
U-0
U-0
—
—
DSCON: DEEP SLEEP CONTROL REGISTER
C = Clearable bit
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
U-0
U-0
—
—
(2)
U = Unimplemented bit, read as ‘0’
HS = Hardware Settable bit
‘0’ = Bit is cleared
U-0
U-0
—
—
(1)
U-0
r-0
—
r
 2010-2011 Microchip Technology Inc.
r = Reserved bit
x = Bit is unknown
DSBOR
R/W-0
U-0
—
(2)
R/C-0, HS
RELEASE
U-0
—
bit 8
bit 0