SST25VF020B-80-4C-SAE-T Microchip Technology, SST25VF020B-80-4C-SAE-T Datasheet
SST25VF020B-80-4C-SAE-T
Specifications of SST25VF020B-80-4C-SAE-T
Related parts for SST25VF020B-80-4C-SAE-T
SST25VF020B-80-4C-SAE-T Summary of contents
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... The 25 series Serial Flash family features a four-wire, SPI compatible inter- face that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. The SST25VF020B devices are enhanced with improved operating frequency and even lower power con- sumption ...
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... The SST25VF020B devices significantly improve performance and reliability, while lowering power consumption. The devices write (Program or Erase) with a single power supply of 2.7-3.6V for SST25VF020B. The total energy consumed is a function of the applied voltage, current, and time of application. Since for any given voltage range, the SuperFlash technology uses less current to pro- gram and has a shorter erase time, the total energy consumed during any Erase or Program operation is less than alternative flash memory technologies ...
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... Functional Block Diagram Figure 1: Functional Block Diagram ©2011 Silicon Storage Technology, Inc. 2 Mbit SPI Serial Flash X - Decoder Address Buffers and Latches Control Logic Serial Interface CE# SCK SST25VF020B Data Sheet SuperFlash Memory Y - Decoder I/O Buffers and Data Latches WP# HOLD# 1417 B1.0 S71417-03-000 02/11 ...
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... The Write Protect (WP#) pin is used to enable/disable BPL bit in the status reg- ister. To temporarily stop serial communication with SPI flash memory without reset- ting the device. To provide power supply voltage: 2.7-3.6V for SST25VF020B 4 2 Mbit SPI Serial Flash SST25VF020B Data Sheet ...
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... Serial Data Input (SI), Serial Data Output (SO), and Serial Clock (SCK). The SST25VF020B supports both Mode 0 (0,0) and Mode 3 (1,1) of SPI bus operations. The difference between the two modes, as shown in Figure 3, is the state of the SCK signal when the bus master is in Stand-by mode and no data is being transferred ...
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... Figure 4: Hold Condition Waveform Write Protection SST25VF020B provides software Write protection. The Write Protect pin (WP#) enables or disables the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the sta- tus register, and the Top/Bottom Sector Protection Status bits (TSP and BSP) in Status Register 1, pro- vide Write protection to the memory array and the status register ...
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... Reserved for future use Top Sector Protection status 1 = Indicates highest sector is write locked 0 = Indicates highest sector is Write accessible Bottom Sector Protection status 1 = Indicates lowest sector is write locked 0 = Indicates lowest sector is Write accessible Reserved for future use 7 SST25VF020B Data Sheet Default at Power-up Read/Write ...
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... Default at power-up for BP1 and BP0 is ‘11’. (All Blocks Protected) ©2011 Silicon Storage Technology, Inc. ), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set Status Register Bit BP1 BP0 Mbit SPI Serial Flash SST25VF020B Data Sheet 1 SST25VF020B FOR 2 Protected Memory Address 2 Mbit None 030000H-03FFFFH 020000H-03FFFFH 000000H-03FFFFH S71417-03-000 T5.0 1417 02/11 ...
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... AAI-Word Program, Sector-Erase, Block-Erase, and Chip-Erase) will not be executed. Upon power-up, the TSP and BSP bits are automatically reset to ‘0’. ©2011 Silicon Storage Technology, Inc. 2 Mbit SPI Serial Flash 9 SST25VF020B Data Sheet S71417-03-000 02/11 ...
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... A Microchip Technology Company Instructions Instructions are used to read, write (Erase and Program), and configure the SST25VF020B. The instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut- ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write- Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed first ...
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... CE# must remain active low for the duration of the Read cycle. See Figure 5 for the Read 0 sequence. CE# MODE 3 MODE 0 SCK SI MSB SO Figure 5: Read Sequence ©2011 Silicon Storage Technology, Inc ADD. ADD. ADD. MSB HIGH IMPEDANCE 11 2 Mbit SPI Serial Flash SST25VF020B Data Sheet N+1 N+2 N+3 N OUT OUT OUT OUT MSB 1417 ReadSeq.0 ...
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... Note Dummy Byte: 8 Clocks Input Dummy Cycle (V Figure 6: High-Speed-Read Sequence ©2011 Silicon Storage Technology, Inc and a dummy byte. CE# must remain active low for the ADD. ADD. ADD. X MSB HIGH IMPEDANCE Mbit SPI Serial Flash SST25VF020B Data Sheet N+1 N+2 N+3 N OUT OUT OUT OUT OUT MSB 1417 HSRdSeq ...
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... Byte-Program operation. See Figure 7 for the Byte-Program sequence. Figure 7: Byte-Program Sequence ©2011 Silicon Storage Technology, Inc. CE# MODE SCK MODE 0 02 ADD. SI MSB MSB HIGH IMPEDANCE Mbit SPI Serial Flash SST25VF020B Data Sheet -A ]. Following the address, the data for the completion ADD. ADD MSB LSB 1417 ByteProg ...
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... Enable-Latch bit (WEL=0) and AAI bit. Then execute the 8-bit DBSY command, 80H, to disable RY/ BY# status during the AAI command. See Figures 9 and 10. ©2011 Silicon Storage Technology, Inc. 2 Mbit SPI Serial Flash -A ] with The Hardware End-of-Write detection method is described in the BP. 14 SST25VF020B Data Sheet BP Fol with A =0, the second 23 ...
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... Figure 8: Enable SO as Hardware RY/BY# During AAI Programming Figure 9: Disable SO as Hardware RY/BY# During AAI Programming ©2011 Silicon Storage Technology, Inc. 2 Mbit SPI Serial Flash CE# MODE SCK MODE MSB HIGH IMPEDANCE SO 1271 EnableSO.0 CE# MODE MODE 0 SCK 80 SI MSB HIGH IMPEDANCE SO 1271 DisableSO.0 15 SST25VF020B Data Sheet S71417-03-000 02/11 ...
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... Check for Flash Busy Status to load next valid 1. Valid commands during AAI programming: AAI command or WRDI command 2. User must configure the SO pin to output Flash Busy status during AAI programming Wait T register to load next valid Mbit SPI Serial Flash SST25VF020B Check for Flash Busy Status to load next valid command ...
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... Silicon Storage Technology, Inc Address bits [ remaining address bits can CE# MODE MODE 0 SCK 20 ADD. SI MSB MSB HIGH IMPEDANCE Mbit SPI Serial Flash SST25VF020B Data Sheet = Most Significant address) are used CE# must be driven high IL IH ADD. ADD. 1417 SecErase.0 S71417-03-000 02/11 ...
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... CE# must be driven high before the instruction is executed. The 64-KByte Block- IL IH. ), remaining address bits can CE# MODE MODE 0 SCK 52 SI MSB HIGH IMPEDANCE SO CE# MODE MODE 0 SCK D8 SI MSB HIGH IMPEDANCE Mbit SPI Serial Flash SST25VF020B - remaining Address bits CE# must ADDR ADDR ADDR MSB 1417 32KBklEr ADDR ADDR ADDR MSB 1417 63KBlkEr ...
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... Figure 16:Read-Status-Register (RDSR) Sequence ©2011 Silicon Storage Technology, Inc. CE# MODE SCK MODE MSB HIGH IMPEDANCE MSB HIGH IMPEDANCE 19 2 Mbit SPI Serial Flash SST25VF020B Data Sheet 1417 ChEr Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out 1417 RDSRseq.0 S71417-03-000 02/11 ...
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... Silicon Storage Technology, Inc MSB HIGH IMPEDANCE CE# MODE MODE 0 SCK 06 SI MSB HIGH IMPEDANCE Mbit SPI Serial Flash SST25VF020B Data Sheet Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MSB Status Register Out 1417 RDSR1seq.0 1417 WREN.0 S71417-03-000 02/11 ...
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... CE# must be driven low before the EWSR instruction is entered and must be driven high before the EWSR instruction is executed. ©2011 Silicon Storage Technology, Inc. 2 Mbit SPI Serial Flash CE# MODE MODE 0 SCK 04 SI MSB HIGH IMPEDANCE SO 1417 WRDI.0 21 SST25VF020B Data Sheet after executing the WRDI BP S71417-03-000 02/11 ...
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... Silicon Storage Technology, Inc. ) prior to the low-to-high transition of the CE# pin at the end of the WRSR MODE 3 MODE MSB MSB HIGH IMPEDANCE ) prior to the low-to-high transition of the CE# pin at the end Mbit SPI Serial Flash SST25VF020B Data Sheet STATUS REGISTER MSB 1417 EWSR.0 S71417-03-000 02/11 ...
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... Read-ID instruction, the 8-bit manufacturer’s ID, BFH, is output from the device. After that, a 16-bit device ID is shifted out on the SO pin. Byte 1, BFH, identifies the manufacturer as SST. Byte 2, 25H, identifies the memory type as SPI Serial Flash. Byte 3, 8CH, identifies the device as SST25VF020B. The instruction sequence is shown in Figure 22. The JEDEC Read ID instruction is terminated by a low to high transition on CE# at any time during data output ...
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... A Microchip Technology Company Read-ID (RDID) The Read-ID instruction (RDID) identifies the devices as SST25VF020B and manufacturer as SST. The device information can be read from executing an 8-bit command, 90H or ABH, followed by address bits [ Following the Read-ID instruction, the manufacturer’ located in address 00000H 23 0 and the device ID is located in address 00001H. Once the device is in Read-ID mode, the manufac- turer’ ...
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... Ambient Temp 0°C to +70°C -40°C to +85°C 1 Input Rise/Fall Time 5ns 25 2 Mbit SPI Serial Flash SST25VF020B Data Sheet 2.7-3.6V 2.7-3.6V Output Load ...
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... V Min to Write Operation 25°C, f=1 Mhz, other pins open) A Description Output Pin Capacitance Input Capacitance Parameter Minimum Specification Endurance Data Retention Latch Mbit SPI Serial Flash SST25VF020B Test Conditions mA CE#=0.1 V /0.9 V @33 MHz, SO=open CE#=0.1 V /0.9 V @80 MHz, SO=open CE#=V DD µ ...
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... Maximum clock frequency for Read Instruction, 03H MHz 2. Maximum Rise and Fall time may be limited Relative to SCK. ©2011 Silicon Storage Technology, Inc. 2 Mbit SPI Serial Flash 33 MHz Parameter Min 13 13 0.1 0 and T requirements SCKH SCKL 27 SST25VF020B Data Sheet 80 MHz Max Min Max Units 33 80 MHz 0.1 V/ns 0.1 V/ ...
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... Silicon Storage Technology, Inc. T CES SCKR MSB HIGH SCKH SCKL CLZ MSB HHH HLS Mbit SPI Serial Flash SST25VF020B Data Sheet T CPH T T CEH CHS T SCKF LSB HIGH-Z T CHZ LSB 1417 SerOut.0 T HHS T HLH T LZ S71417-03-000 1417 SerIn.0 1417 Hold.0 02/11 ...
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... DD V Min to Write Operation DD DD Chip selection is not allowed. Commands may not be accepted or properly interpreted by the device Mbit SPI Serial Flash SST25VF020B ramp rate of greater than 1V per 100 DD Minimum 100 100 PU-READ Device fully accessible PU-WRITE 1417 PwrUp.0 S71417-03-000 Data Sheet Units µ ...
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... Silicon Storage Technology, Inc. Min Falling Time 1 DD Rising Time 0.033 DD Off Time 100 DD Off Level OFF GND Mbit SPI Serial Flash SST25VF020B Limits Max Units Conditions 100 ms/V 100 ms (recommended) 1417 F28.0 OFF S71417-03-000 Data Sheet T17.0 1417 02/11 ...
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... INPUT REFERENCE POINTS V LT (0.9V ) for a logic “1” and V IHT DD ↔ 90%) are <5 ns. TO TESTER TO DUT 31 2 Mbit SPI Serial Flash SST25VF020B V HT OUTPUT V LT 1417 IORef.0 (0.1V ) for a logic “0”. Measure- ILT DD (0.6V ) and V (0.4V ). Input rise and ...
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... A Microchip Technology Company Product Ordering Information SST Valid combinations for SST25VF020B SST25VF020B-80-4C-QAE SST25VF020B-80-4I-QAE Note:Valid combinations are those products in mass production or will be in mass production. Consult your SST sales representative to confirm availability of valid combinations and to determine availability of new combinations. ©2011 Silicon Storage Technology, Inc. ...
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... SST Package Code: SA ©2011 Silicon Storage Technology, Inc. 2 Mbit SPI Serial Flash SIDE VIEW 7° 4 places 0.51 0.33 1.27 BSC END VIEW 45° 0.25 0.10 1.75 0.25 1.35 0.19 08-soic-5x6-SA-8 1mm 33 SST25VF020B Data Sheet 7° 4 places 0° 8° 1.27 0.40 S71417-03-000 02/11 ...
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... Silicon Storage Technology, Inc. SIDE VIEW 0.2 5.00 0.10 0.076 0.05 Max 0.80 0.70 leads. 1mm SS of the unit Mbit SPI Serial Flash SST25VF020B Data Sheet BOTTOM VIEW Pin #1 1.27 BSC 4.0 0.48 0.35 3.4 0.70 0.50 CROSS SECTION 0.80 0.70 8-wson-5x6-QA-9.0 ...
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... Write Detection”, and “Hardware End-of-Write Detection” on page 14. Revised Figures 10 and 11 on page page 16. Updated document to new format. Silicon Storage Technology, Inc. A Microchip Technology Company www.microchip.com or www.sst.com 35 2 Mbit SPI Serial Flash SST25VF020B Data Sheet Date Dec 2009 Feb 2010 Apr 2010 Feb 2011 S71417-03-000 ...