SST25VF020B-80-4C-SAE-T Microchip Technology, SST25VF020B-80-4C-SAE-T Datasheet - Page 10

• Manufacturer Part Number: SST25VF020B-80-4C-SAE-T
• Description: 2.7V To 3.6V 2Mbit SPI Serial Flash 8 SOIC 3.90mm (.150") T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF020B-80-4C-SAE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Instructions
Instructions are used to read, write (Erase and Program), and configure the SST25VF020B. The
instruction bus cycles are 8 bits each for commands (Op Code), data, and addresses. Prior to execut-
ing any Byte-Program, Auto Address Increment (AAI) programming, Sector-Erase, Block-Erase, Write-
Status-Register, or Chip-Erase instructions, the Write-Enable (WREN) instruction must be executed
first. The complete list of instructions is provided in Table 6. All instructions are synchronized off a high
to low transition of CE#. Inputs will be accepted on the rising edge of SCK starting with the most signif-
icant bit. CE# must be driven low before an instruction is entered and must be driven high after the last
bit of the instruction has been shifted in (except for Read, Read-ID, and Read-Status-Register instruc-
tions). Any low to high transition on CE#, before receiving the last bit of an instruction bus cycle, will
terminate the instruction in progress and return the device to standby mode. Instruction commands
(Op Code), addresses, and data are all input from the most significant bit (MSB) first.
Table 6: Device Operation Instructions
Instruction
Read
High-Speed Read
4 KByte Sector-Erase
32 KByte Block-Erase
64 KByte Block-Erase
Chip-Erase
Byte-Program
AAI-Word-Program
RDSR
RDSR1
EWSR
WRSR
WREN
WRDI
RDID
JEDEC-ID
EBSY
DBSY
1. One bus cycle is eight clock periods.
2. Address bits above the most significant bit of each density can be V
3. 4KByte Sector Erase addresses: use A
4. 32KByte Block Erase addresses: use A
5. 64KByte Block Erase addresses: use A
6. To continue programming to the next sequential address location, enter the 8-bit command, ADH, followed by 2 bytes of
7. The Read-Status-Register is continuous with ongoing clock cycles until terminated by a low to high transition on CE#.
8. Manufacturer’s ID is read with A
data to be programmed. Data Byte 0 will be programmed into the initial address [A
programmed into the
initial address [A
turer’s ID and device ID output stream is continuous until terminated by a low-to-high transition on CE#.
8
7
6
3
4
5
23
-A
Description
Read Memory
Read Memory at higher speed
Erase 4 KByte of memory array
Erase 32 KByte block of memory array 0101 0010b (52H)
Erase 64 KByte block of memory array 1101 1000b (D8H)
Erase Full Memory Array
To Program One Data Byte
Auto Address Increment Programming 1010 1101b (ADH)
Read-Status-Register
Read-Status-Register 1
Enable-Write-Status-Register
Write-Status-Register
Write-Enable
Write-Disable
Read-ID
JEDEC ID read
Enable SO to output RY/BY# status
during AAI programming
Disable SO as RY/BY#
status during AAI programming
1
] with A
0
=1.
0
=0, and Device ID is read with A
MS
MS
MS
-A
-A
-A
10
12,
15,
16,
remaining addresses are don’t care but must be set either at V
remaining addresses are don’t care but must be set either at V
remaining addresses are don’t care but must be set either at V
Op Code Cycle
0000 0011b (03H)
0000 1011b (0BH)
0010 0000b (20H)
0110 0000b (60H) or
1100 0111b (C7H)
0000 0010b (02H)
0000 0101b (05H)
0011 0101b (35H)
0101b 0000b (50H)
0000 0001b (01H)
0000 0110b (06H)
0000 0100b (04H)
1001 0000b (90H) or
1010 1011b (ABH)
1001 1111b (9FH)
0111 0000b (70H)
1000 0000b (80H)
0
2 Mbit SPI Serial Flash
=1. All other address bits are 00H. The Manufac-
IL
or V
IH
.
1
23
Cycle(s)
-A
Address
1
] with A
3
3
3
3
3
0
3
3
0
0
0
0
0
0
3
0
0
0
SST25VF020B
2
0
=0, Data Byte 1 will be
Cycle(s)
Dummy
S71417-03-000
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Data Sheet
Cycle(s)
IL
IL
IL
1 to ∞
1 to ∞
2 to ∞
1 to ∞
1 to ∞
1 or 2
1 to ∞
3 to ∞
T6.0 1417
or V
Data
or V
or V
0
0
0
0
1
0
0
0
0
0
IH.
IH.
IH.
02/11