SST25VF020B-80-4C-SAE-T Microchip Technology, SST25VF020B-80-4C-SAE-T Datasheet - Page 8

• Manufacturer Part Number: SST25VF020B-80-4C-SAE-T
• Description: 2.7V To 3.6V 2Mbit SPI Serial Flash 8 SOIC 3.90mm (.150") T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF020B-80-4C-SAE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Busy
Write Enable Latch (WEL)
Auto Address Increment (AAI)
Block Protection (BP1, BP0)
Block Protection Lock-Down (BPL)
The Busy bit determines whether there is an internal Erase or Program operation in progress. A “1” for
the Busy bit indicates the device is busy with an operation in progress. A “0” indicates the device is
ready for the next valid operation.
The Write-Enable-Latch bit indicates the status of the internal memory Write Enable Latch. If the
Write-Enable-Latch bit is set to “1”, it indicates the device is Write enabled. If the bit is set to “0” (reset),
it indicates the device is not Write enabled and does not accept any memory Write (Program/Erase)
commands. The Write-Enable-Latch bit is automatically reset under the following conditions:
The Auto Address Increment Programming-Status bit provides status on whether the device is in AAI
programming mode or Byte-Program mode. The default at power up is Byte-Program mode.
The Block-Protection (BP1, BP0) bits define the size of the memory area, as defined in Table 5, to be
software protected against any memory Write (Program or Erase) operation. The Write-Status-Regis-
ter (WRSR) instruction is used to program the BP1 and BP0 bits as long as WP# is high or the Block-
Protect-Lock (BPL) bit is 0. Chip-Erase can only be executed if Block-Protection bits are all 0. After
power-up, BP1 and BP0 are set to 1.
WP# pin driven low (V
prevents any further alteration of the BPL, BP1, and BP0 bits of the status register and BSP and TSP
of Status Register 1. When the WP# pin is driven high (VIH), the BPL bit has no effect and its value is
“Don’t Care”. After power-up, the BPL bit is reset to 0.
Table 5: Software Status Register Block Protection
Protection Level
1. X = Don’t Care (RESERVED) default is “0
2. Default at power-up for BP1 and BP0 is ‘11’. (All Blocks Protected)
0
1 (1/4 Memory Array)
1 (1/2 Memory Array)
1 (Full Memory Array)
•
•
•
•
•
•
•
•
Power-up
Write-Disable (WRDI) instruction completion
Byte-Program instruction completion
Auto Address Increment (AAI) programming is completed or reached its highest unpro-
tected memory address
Sector-Erase instruction completion
Block-Erase instruction completion
Chip-Erase instruction completion
Write-Status-Register instructions
IL
), enables the Block-Protection-Lock-Down (BPL) bit. When BPL is set to 1, it
8
Status Register Bit
BP1
0
0
1
1
BP0
0
1
0
1
2 Mbit SPI Serial Flash
FOR
2
SST25VF020B
Protected Memory Address
030000H-03FFFFH
020000H-03FFFFH
000000H-03FFFFH
SST25VF020B
2 Mbit
1
None
S71417-03-000
Data Sheet
T5.0 1417
02/11