SST25VF020B-80-4C-SAE-T Microchip Technology, SST25VF020B-80-4C-SAE-T Datasheet - Page 20

2.7V To 3.6V 2Mbit SPI Serial Flash 8 SOIC 3.90mm (.150") T/R

SST25VF020B-80-4C-SAE-T

Manufacturer Part Number
SST25VF020B-80-4C-SAE-T
Description
2.7V To 3.6V 2Mbit SPI Serial Flash 8 SOIC 3.90mm (.150") T/R
Manufacturer
Microchip Technology
Datasheet

Specifications of SST25VF020B-80-4C-SAE-T

Format - Memory
FLASH
Memory Type
FLASH
Memory Size
2M (256K x 8)
Speed
80MHz
Interface
SPI Serial
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (0.154", 3.90mm Width)
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
A Microchip Technology Company
©2011 Silicon Storage Technology, Inc.
Read-Status-Register (RDSR1)
Write-Enable (WREN)
The Read-Status-Register 1 (RDSR1) instruction allows reading of the status register 1. CE# must be
driven low before the RDSR instruction is entered and remain low until the status data is read. Read-
Status-Register 1 is continuous with ongoing clock cycles until it is terminated by a low to high transi-
tion of the CE#. See Figure 17 for the RDSR instruction sequence.
Figure 17:Read-Status-Register 1 (RDSR1) Sequence
The Write-Enable (WREN) instruction sets the Write-Enable-Latch bit in the Status Register to 1 allow-
ing Write operations to occur. The WREN instruction must be executed prior to any Write (Program/
Erase) operation. The WREN instruction may also be used to allow execution of the Write-Status-Reg-
ister (WRSR) instruction; however, the Write-Enable-Latch bit in the Status Register will be cleared
upon the rising edge CE# of the WRSR instruction. CE# must be driven high before the WREN instruc-
tion is executed.
SCK
CE#
SO
SI
MODE 3
MODE 0
MSB
0
1
HIGH IMPEDANCE
2
SCK
CE#
SO
SI
3
35
MODE 3
MODE 0
4
20
5
HIGH IMPEDANCE
MSB
0 1 2 3 4 5 6 7
6
7
06
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
MSB
8
2 Mbit SPI Serial Flash
1417 WREN.0
9
10
Register Out
11
Status
12
SST25VF020B
13
1417 RDSR1seq.0
14
S71417-03-000
Data Sheet
02/11

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