SST25VF020B-80-4C-SAE-T Microchip Technology, SST25VF020B-80-4C-SAE-T Datasheet - Page 6

• Manufacturer Part Number: SST25VF020B-80-4C-SAE-T
• Description: 2.7V To 3.6V 2Mbit SPI Serial Flash 8 SOIC 3.90mm (.150") T/R
• Manufacturer: Microchip Technology

Specifications of SST25VF020B-80-4C-SAE-T

• Format - Memory: FLASH
• Memory Type: FLASH
• Memory Size: 2M (256K x 8)
• Speed: 80MHz
• Interface: SPI Serial
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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©2011 Silicon Storage Technology, Inc.
Hold Operation
Write Protection
Write Protect Pin (WP#)
The HOLD# pin is used to pause a serial sequence underway with the SPI flash memory without reset-
ting the clocking sequence. To activate the HOLD# mode, CE# must be in active low state. The HOLD#
mode begins when the SCK active low state coincides with the falling edge of the HOLD# signal. The
HOLD mode ends when the HOLD# signal’s rising edge coincides with the SCK active low state.
If the falling edge of the HOLD# signal does not coincide with the SCK active low state, then the device
enters Hold mode when the SCK next reaches the active low state. Similarly, if the rising edge of the
HOLD# signal does not coincide with the SCK active low state, then the device exits in Hold mode
when the SCK next reaches the active low state. See Figure 4 for Hold Condition waveform.
Once the device enters Hold mode, SO will be in high-impedance state while SI and SCK can be V
V
If CE# is driven high during a Hold condition, the device returns to Standby mode. As long as HOLD#
signal is low, the memory remains in the Hold condition. To resume communication with the device,
HOLD# must be driven active high, and CE# must be driven active low. See Figure 4 for Hold timing.
Figure 4: Hold Condition Waveform
SST25VF020B provides software Write protection. The Write Protect pin (WP#) enables or disables
the lock-down function of the status register. The Block-Protection bits (BP1, BP0, and BPL) in the sta-
tus register, and the Top/Bottom Sector Protection Status bits (TSP and BSP) in Status Register 1, pro-
vide Write protection to the memory array and the status register. See Table 5 for the Block-Protection
description.
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined
by the value of the BPL bit (see Table 2). When WP# is high, the lock-down function of the BPL bit is
disabled.
Table 2: Conditions to execute Write-Status-Register (WRSR) Instruction
HOLD#
IH.
SCK
WP#
H
L
L
Active
BPL
X
1
0
6
Hold
Execute WRSR Instruction
Not Allowed
Allowed
Allowed
2 Mbit SPI Serial Flash
Active
Hold
SST25VF020B
S71417-03-000
Active
Data Sheet
1417 HoldCond.0
T2.0 1417
IL
02/11
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