SAA7118E NXP Semiconductors, SAA7118E Datasheet - Page 117

SAA7118E

Manufacturer Part Number
SAA7118E
Description
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SAA7118E

Adc/dac Resolution
9b
Screening Level
Commercial
Package Type
LBGA
Pin Count
156
Lead Free Status / RoHS Status
Compliant

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NXP Semiconductors
Table 59.
Table 60.
Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; see
SAA7118_7
Product data sheet
Bit
D7
D6
23h[7] and
14h[5:4]
D3
D2
D[1:0]
Field
50 Hz
60 Hz
1st
2nd
1st
2nd
1st
2nd
1st
2nd
1st
2nd
1st
2nd
Analog/ADC/auto/compatibility control; 14h[7:0]
VGATE start; FID polarity change; 17h[0] and 15h[7:0]
10.2.21 Subaddress 14h
10.2.22 Subaddress 15h
Description
compatibility bit for SAA7199
update time interval for AGC
value
analog test select
XTOUT output enable
automatic chrominance
standard detection control 1
ADC sample clock phase
delay
Frame
line
counting
1
314
2
315
312
625
4
267
5
268
265
3
Decimal
value
312
0...
...310
262
0...
...260
MSB
17h[0]
VSTA8
1
0
1
1
0
1
Symbol
CM99
UPTCV
AOSL[2:0]
XTOUTE
AUTO1
APCK[1:0]
Control bits D7 to D0
VSTA7 VSTA6 VSTA5 VSTA4 VSTA3 VSTA2 VSTA1 VSTA0
0
0
0
0
0
0
Rev. 07 — 7 July 2008
Multistandard video decoder with adaptive comb filter
0
0
0
0
0
0
Value
0
1
0
1
000
001
010
011
100
101
110
111
0
1
see
00
01
10
11
Section 10.2.15
1
0
1
0
0
0
Function
off (default)
on (to be set only if SAA7199 is used for
re-encoding in conjunction with RTCO active)
horizontal update (once per line)
vertical update (once per field)
AOUT connected to ground
AOUT connected to input AD1
AOUT connected to input AD2
AOUT connected to input AD3
AOUT connected to input AD4
reserved
reserved
AOUT connected to internal test point BPFOUT
XTOUT 3-stated
XTOUT enabled
application dependent
application dependent
application dependent
application dependent
1
0
1
0
0
0
1
0
0
0
0
0
Figure 32
0
0
1
1
0
1
SAA7118
© NXP B.V. 2008. All rights reserved.
0
0
1
1
0
0
and
Figure
117 of 177
0
0
1
0
0
1
33.

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