SAA7118E NXP Semiconductors, SAA7118E Datasheet - Page 135

• Manufacturer Part Number: SAA7118E
• Manufacturer: NXP Semiconductors

Specifications of SAA7118E

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
Table 113. X port input reference signal definitions; register set A [92h[7:4]] and B [C2h[7:4]]
[1]
Table 114. X port input reference signal definitions; register set A [92h[3:0]] and B [C2h[3:0]]
[1]
Table 115. I port output format and configuration; register set A [93h[7:5]] and B [C3h[7:5]]
[1]
SAA7118_7
Product data sheet
X port input reference signal definitions
XRV is a frame sync, V pulses are generated internally on both
edges of FS input
X port field ID is state of XRH at reference edge on XRV (defined by
XFDV)
Field ID (decoder and X port field ID) is inverted
Reference edge for field detection is falling edge of XRV
Reference edge for field detection is rising edge of XRV
X port input reference signal definitions
XCLK input clock and XDQ input qualifier are needed
Data rate is defined by XCLK only, no XDQ signal used
Data are qualified at XDQ input at logic 1
Data are qualified at XDQ input at logic 0
Rising edge of XRH input is horizontal reference
Falling edge of XRH input is horizontal reference
Reference signals are taken from XRH and XRV
Reference signals are decoded from EAV and SAV
I port output formats and configuration
All lines will be output
Skip the number of leading Y only lines, as defined by FOI1 and
FOI0
Double words are transferred byte wise, see subaddress 85h
bits ISWP1 and ISWP0
Double words are transferred 16-bit word wise via IPD and HPD,
see subaddress 85h bits ISWP1 and ISWP0
No ITU 656 like SAV/EAV codes are available
ITU 656 like SAV/EAV codes are inserted in the output data stream,
framed by a qualifier
X = don’t care.
X = don’t care.
X = don’t care.
Rev. 07 — 7 July 2008
Multistandard video decoder with adaptive comb filter
Control bits D7 to D4
XFDV
X
X
X
0
1
Control bits D3 to D0
XCODE
X
X
X
X
X
X
0
1
Control bits D7 to D5
ICODE
X
X
X
X
0
1
XFDH
X
0
1
X
X
XDH
X
X
X
X
0
1
X
X
I8_16
X
X
0
1
X
X
XDV1
1
X
X
X
X
XDQ
X
X
0
1
X
X
X
X
[1]
[1]
[1]
…continued
SAA7118
© NXP B.V. 2008. All rights reserved.
FYSK
0
1
X
X
X
X
XDV0
X
X
X
X
X
XCKS
0
1
X
X
X
X
X
X
135 of 177