SAA7118E NXP Semiconductors, SAA7118E Datasheet - Page 73

• Manufacturer Part Number: SAA7118E
• Manufacturer: NXP Semiconductors

Specifications of SAA7118E

• Adc/dac Resolution: 9b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

NXP Semiconductors
SAA7118_7
Product data sheet
9.4.1.3 VBI data slicer
9.4.1.4 Scaler
9.4.2 Status reading conditions
9.4.3 Erasing conditions
9.5 Video expansion port (X port)
FIDT: detected field frequency has changed (50 Hz
RDCAP: ready for capture (true
DCSTD[1:0]: detected color standard has changed or color lost.
COPRO, COLSTR and TYPE3: various levels of copy protection have changed.
VPSV: VPS identification found or lost.
PPV: PALplus identification found or lost.
CCV: Closed caption identification found or lost.
ERROF: scaler output formatting error detected.
The status information read after an interrupt will always be the LATEST state, that means
the status will not be ‘frozen’ when an interrupt is being generated. Therefore, if there is a
long time between interrupt generation and status reading, the original trigger condition
might have been overridden by the present state.
The status flags are grouped into four 8-bit registers.
The interrupt flag will only be cleared on a read access to the status register in which the
signal is located which caused the interrupt. This implies that it is sufficient to clear the
interrupt by reading only those registers which have been enabled by their corresponding
masks.
Priority: If a new trigger condition occurs at the SAME time (clock) on which a status is
being read, the flag will NOT be cleared.
The expansion port is intended for transporting video streams image data from other
digital video circuits such as MPEG encoder/decoder and video phone codec, to the
image port (I port).
The expansion port consists of two groups of signals/pins:
As output, these are direct copies of the decoder signals.
The data transfers through the expansion port represent a single D1 port, with half duplex
mode. The SAV and EAV codes may be inserted optionally for data input (controlled by
bit XCODE[92h[3]]). The input/output direction is switched for complete fields only.
•
•
8-bit data, I/O, regularly components video Y-C
serial, exceptionally raw video samples (e.g. ADC test); in input mode the data bus
can be extended to 16-bit by pins HPD7 to HPD0
Clock, synchronization and auxiliary signals, accompanying the data stream, I/O
Rev. 07 — 7 July 2008
Multistandard video decoder with adaptive comb filter
false).
B
-C
R
60 Hz).
4 : 2 : 2, i.e. C
SAA7118
B
© NXP B.V. 2008. All rights reserved.
-Y-C
R
-Y, byte
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