SAA7105E/V1/G.557 NXP Semiconductors, SAA7105E/V1/G.557 Datasheet - Page 14

• Manufacturer Part Number: SAA7105E/V1/G.557
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G.557

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
7.12.2 Teletext insertion and encoding (not simultaneously with real-time control)
7.12.3 Video Programming System (VPS) encoding
7.12.4 Closed caption encoder
7.12.5 Anti-taping (SAA7104E only)
Chrominance is modified in gain (programmable separately for C
standard dependent burst is inserted, before baseband color signals are interpolated from
a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be
bypassed, thus providing a higher color bandwidth, which can be used for the Y and C
output. The transfer characteristics of the chrominance interpolation filter are illustrated in
Figure 6
The amplitude (beginning and ending) of the inserted burst, is programmable in a certain
range that is suitable for standard signals and for special effects. After the succeeding
quadrature modulator, color is provided on the subcarrier in 10-bit resolution.
The numeric ratio between the Y and C outputs is in accordance with the standards.
Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock.
At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided
after a programmable delay at input pin TTX_SRES.
Phase variant interpolation is achieved on this bitstream in the internal teletext encoder,
providing sufficient small phase jitter on the output text lines.
TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source,
indicating the insertion period of bitstream at lines which can be selected independently
for both fields. The internal insertion window for text is set to 360 (PAL WST),
296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol
and timing are illustrated in
Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz.
Five bytes of VPS information can be loaded via the I
appropriate format into line 16.
Using this circuit, data in accordance with the specification of closed caption or extended
data service, delivered by the control interface, can be encoded (line 21). Two dedicated
pairs of bytes (two bytes per field), each pair preceded by run-in clocks and framing code,
are possible.
The actual line number in which data is to be encoded, can be modified in a certain range.
The data clock frequency is in accordance with the definition for NTSC M standard
32 times horizontal line frequency.
Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the
DACs corresponds to approximately 50 IRE.
It is also possible to encode closed caption data for 50 Hz field frequencies at 32 times the
horizontal line frequency.
For more information contact your nearest Philips Semiconductors sales office.
and
Figure
7.
Rev. 02 — 23 December 2005
Figure
15.
SAA7104E; SAA7105E
2
C-bus and will be encoded in the
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
B
and C
Digital video encoder
R
), and a
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