SAA7105E/V1/G.557 NXP Semiconductors, SAA7105E/V1/G.557 Datasheet - Page 54

• Manufacturer Part Number: SAA7105E/V1/G.557
• Manufacturer: NXP Semiconductors

Specifications of SAA7105E/V1/G.557

• Adc/dac Resolution: 10b
• Screening Level: Commercial
• Package Type: LBGA
• Pin Count: 156
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
SAA7104E_SAA7105E_2
Product data sheet
Table 92:
Table 93:
Table 94:
Table 95:
Table 96:
Table 97:
Legend: * = default value after reset.
Bit
7 to 4
3 and 2 HLPPT[1:0] state of the HD pattern pointer after trigger
1 and 0 HLCT[9:8]
Bit
7 to 0
Bit
7
6 to 4
3 and 2 -
1 and 0 HDCT[9:8] see
Subaddress Bit
D9h
D8h
Subaddress Bit
DBh
DAh
Bit
7 to 4
3
2
Symbol
HLCPT[3:0] state of the HD line type pointer after trigger
Symbol
HDCT[7:0] with HDCT[9:8] (see
Symbol
-
HEPT[2:0] state of the HD event type pointer in the line type array after trigger
Symbol Access Value Description
-
HDSYE R/W
HDTC
HD sync trigger state 2 register, subaddress D5h, bit description
HD sync trigger state 3 register, subaddress D6h, bit description
HD sync trigger state 4 register, subaddress D7h, bit description
HD sync trigger phase x registers, subaddresses D8h and D9h, bit description
HD sync trigger phase y registers, subaddresses DAh and DBh, bit description
HD output control register, subaddress DCh, bit description
7 to 4 -
3 to 0 HTX[11:8] horizontal trigger phase for the HD sync engine in pixel clocks
7 to 0 HTX[7:0]
7 to 2
1 and 0 HTY[9:8] vertical trigger phase for the HD sync engine in input lines
7 to 0
R/W
R/W
Description
(counts backwards)
Description
must be programmed with logic 0 to ensure compatibility to future
enhancements
must be programmed with logic 0 to ensure compatibility to future
enhancements
Symbol
Rev. 02 — 23 December 2005
Description
see
Symbol
-
HTY[7:0]
Table 93
Table 91
0
0*
1
0*
1
Description
must be programmed with logic 0 to ensure compatibility to
future enhancements
Description
must be programmed with logic 0 to ensure compatibility to
future enhancements
must be programmed with logic 0 to ensure compatibility to
future enhancements
HD sync engine
off
active
HD output path processes
RGB
YUV
Table
SAA7104E; SAA7105E
94) state of the HD duration counter after trigger
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Digital video encoder
54 of 78