AD1847JP Analog Devices Inc, AD1847JP Datasheet - Page 17

• Manufacturer Part Number: AD1847JP
• Manufacturer: Analog Devices Inc

Specifications of AD1847JP

• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PLCC
• Lead Free Status / RoHS Status: Not Compliant

REV. B
Miscellaneous Information Register (Index Address 12)
The Miscellaneous Information Register can only be changed when the AD1847 is in the Mode Change Enable (MCE) state. Changes to this
register are updated at the next Serial Data Frame Sync (SDFS) boundary. If FRS is LO (i.e., 32 slots per frame), and either TSSEL or FRS
change in the first sample of a frame, the change is not updated at the second sample of the same frame, but at the first sample of the next frame.
TSSEL
FRS
res
This register’s initial state after reset is: 0000 0000 (00h).
Digital Mix Control Register (Index Address 13)
DME
DMA5:0
res
This register’s initial state after reset is: 0000 0000 (00h).
Invalid Address (Index Address 14)
inval
Invalid Address (Index Address 15)
inval
IA3:0
1101
IA3:0
IA3:0
IA3:0
1100
1110
1111
Transmit Slot Select. This bit determines which TDM time slots the AD1847 should transmit on.
0
1
Frame Size. This bit selects the number of time slots per frame.
0
1
Reserved for future expansion. Write zeros (LO) to all reserved bits.
Digital Mix Enable. This bit enables the digital mix of the ADCs’ output with the DACs’ input. When enabled, the data
from the ADCs is digitally mixed with other data being delivered to the DACs (regardless of whether or not playback
[PEN] is enabled, i.e., set). If there is a capture overrun, then the last sample captured before overrun will be used for
the digital mix. If playback is enabled (PEN set) and there is a playback underrun, then a midscale zero will be added to
the digital mix data.
0
1
Digital Mix Attenuation. These bits determine the attenuation of the ADC output data mixed with the DAC input data.
The least significant bit of this 64-level attenuate select represents –1.5 dB. Maximum attenuation is –94.5 dB.
Reserved for future expansion. Write zeros (LO) to all reserved bits.
Writes to this index address are ignored. Index readback of this index address will return the Status Word.
Writes to this index address are ignored. Index readback of this index address will return the Status Word.
Data 7
DMA5
Data 7
Data 7
Data 7
inval
inval
FRS
Transmit on time slots 3, 4 and 5. Used when SDI and SDO are tied together (i.e., “1-wire” system).
Transmit on slots 0, 1 and 2. Used when SDI and SDO are independent inputs and outputs
(i.e., “2-wire” system).
Selects 32 slots per frame (two samples per frame sync or frame sync at half the sample rate).
Selects 16 slots per frame (one sample per frame sync or frame sync at the sample rate).
Digital mix disabled (muted)
Digital mix enabled
Data 6
DMA4
TSSEL
Data 6
Data 6
Data 6
inval
inval
Data 5
DMA3
Data 5
Data 5
Data 5
inval
inval
res
Data 4
DMA2
Data 4
Data 4
Data 4
inval
inval
res
–17–
DMA1
Data 3
Data 3
Data 3
Data 3
inval
inval
res
Data 2
DMA0
Data 2
Data 2
Data 2
inval
inval
res
Data 1
Data 1
Data 1
Data 1
res
inval
inval
res
Data 0
DME
Data 0
Data 0
Data 0
AD1847
inval
inval
res