AD1847JP Analog Devices Inc, AD1847JP Datasheet - Page 22

• Manufacturer Part Number: AD1847JP
• Manufacturer: Analog Devices Inc

Specifications of AD1847JP

• Single Supply Voltage (typ): 5V
• Single Supply Voltage (min): 4.75V
• Single Supply Voltage (max): 5.25V
• Package Type: PLCC
• Lead Free Status / RoHS Status: Not Compliant

AD1847
When the AD1847 is in bus slave mode (BM = LO), the TSI
pin should be connected to the TSO pin of the AD1847 master
or slave which has been assigned to the preceding time slots.
The signal on the TSO pin is essentially the signal received on
the TSI pin, but delayed by 3 or 6 time slots from TSI (depend-
ing on the state of TSSEL). The frequency of the transitions on
the TSI and TSO lines is equivalent to the frequency on the
SDFS pin.
When the AD1847 is in bus master mode (BM = HI), the TSI
pin should be connected to digital ground. The signal on the
TSO pin is essentially the same as the signal output on the
SDFS pin, but delayed by 3 or 6 time slots from SDFS (again,
depending on the state of TSSEL).
Mode Change Enable State
The AD1847 must be in the Mode Change Enable (MCE) state
before any changes to the ACAL bit of the Interface Configura-
tion Register, the Data Format Register, or the Miscellaneous
Information Register are allowed. Note that the MCE bit does
not have to be reset LO in order for changes to take effect.
Digital Mix
Digital mix is enabled via the DME bit in the Digital Mix Con-
trol Register. The digital mix routes the digital data from the
ADCs to the DACs. The mix can be digitally attenuated via bits
also in the Digital Mix Control Register. The ADC data is
summed with the DAC data supplied at the digital bus inter-
face. When digital mix is enabled and the PEN bit is not set,
ADC data is summed with zeros to produce the DAC output.
If the sum of the digital mix (ADC output and DAC input from
the serial bus interface) is greater than full scale, the AD1847
will send a positive or negative full scale value to the DACs,
whichever is appropriate (clipping).
Autocalibration
The AD1847 has the ability to calibrate its ADCs and DACs for
greater accuracy by minimizing dc offsets. Autocalibration oc-
curs whenever the AD1847 exits from the Mode Change Enable
(MCE) state AND the ACAL bit in the Interface Configuration
Register has been set.
The completion of the autocalibration sequence can be deter-
mined by polling the Autocalibration In-Progress (ACI) bit in
the Status Word. This bit will be HI while the autocalibration is
in progress and LO once autocalibration has completed. The
autocalibration sequence will take at least 384 sample periods.
The autocalibration procedure is as follows:
1. Mute both left and right AUX1 and AUX2 inputs via the Left
2. Place the AD1847 in the Mode Change Enable (MCE) state
3. Exit from the Mode Change Enable state by resetting the
4. Poll the ACI bit in the AD1847 Status Word for a HI
5. Unmute the AUX inputs, if used.
Auxiliary Input and Right Auxiliary Input Control Registers.
using the MCE bit of the AD1847 Control Word. Set the
ACAL bit in the Interface Configuration Register.
MCE bit.
(autocalibration in progress), then poll the ACI bit for a LO
(autocalibration complete).
–22–
If ACAL is not set, the AD1847 is muted for 128 sample peri-
ods after resetting the MCE bit, and the ACI bit in the Status
Word is set HI during this 128 sample periods. Autocalibration
must be performed after power-up to ensure proper operation of
the AD1847.
Exiting from the MCE state always causes ACI to go HI. If the
ACAL bit is set when MCE state is exited, then the ACI bit will
be HI for 384 sample periods. If the ACAL bit is reset when
MCE is exited, then the ACI bit will be HI for 128 sample
periods.
Changing Sample Rates
The internal states of the AD1847 are synchronized by the
selected sample frequency defined in the Data Format Register.
The changing of either the clock source or the clock frequency
divide requires a special sequence for proper AD1847 operation.
1. Mute the outputs of the AD1847 and enter the Mode Change
2. During a single atomic or nondivisible write cycle, change the
3. The INIT bit in the Status Word will be set HI at the last
4. The AD1847 requires a period of time to resynchronize its
5. Exit the Mode Change Enable state by resetting the MCE bit.
6. Poll the ACI bit in the AD1847 Status Word for a HI (indi-
The CSL and CFS bits cannot be changed unless the AD1847
is in the Mode Change Enable state (i.e., the MCE bit in the
AD1847 Control Word is set). Attempts to change the contents
of the Data Format Register without MCE set will result in the
write cycle not being recognized (the bits will not be updated).
The MCE bit should not be reset until after the INIT bit in the
AD1847 Status Word is detected HI. After the INIT bit is de-
tected HI, the serial port is disabled. When the next frame sync
arrives (after the time-out period), all internal clocks are stable
and the serial port is ready for normal operation.
Enable (MCE) state by setting the MCE bit of the AD1847
Control Word.
Clock Frequency Divide Select (CFS) and/or the Clock
Source Select (CSL) bits of the Data Format Register to the
desired values. CFS and CSL can be programmed in the
same Control Word as MCE.
sample of the next frame to indicate that the serial port will be
disabled for a timeout period.
internal states to the newly selected clock. During this time,
the AD1847 will be unable to respond at its serial interface
port (i.e., no frame syncs will be generated). The time-out
period is 2
for subsequent changes of sample rate.
Upon exiting the MCE state, an autocalibration of duration
384 sample periods or an output mute of duration 128 sample
periods occurs, depending on the state of the ACAL bit.
cating that autocalibration is in progress) then poll the ACI
bit for a LO (indicating that autocalibration has completed).
Once the ACI bit has been read back LO, normal operation of
the Codec can resume.
21
SCLK
170 ms after power-up, and 5 ms
REV. B