CP82C37A-5 Intersil, CP82C37A-5 Datasheet - Page 14

• Manufacturer Part Number: CP82C37A-5
• Manufacturer: Intersil

Specifications of CP82C37A-5

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Lead Free Status / RoHS Status: Not Compliant

Figure 7 shows an application for a DMA system using the
82C37A DMA controller and the 80C286 Microprocessor.
In this application, the system clock comes from the 82C284
clock generator PCLK signal which is inverted to provide
proper READY setup and hold times to the DMA controller in
an 80C286 system. The Read and Write signals from the
DMA controller may be wired directly to the Read/Write
control signals from the 82C288 Bus Controller. The octal
CLK
82C288
READY
CLK
MWTC
MRDC
IOWC
IORC
82C284
80C286
READY
PCLK
CLK
A0-A23
D0-D15
HLDA
HLD
IOR
IOW
MEMR
MEMW
14
DECODE
STB
OE
LATCH
ADSTB
HRQ
HLDA
CLK
READY
FIGURE 7. 80C286 DMA APPLICATION
AEN
TRANS-
CEIVER
D0-D7
EOP
V
CHIP SELECT
TO MEMORY/
PERIPHERALS
CC
DREQ 0-3
82C37A
82C37A
D0-D7
TRANS-
CEIVER
latch for A8-A15 from the DMA controller’s data bus is on the
local 80C286 address bus so that memory chip selects may
still be generated during DMA transfers. The transceiver on
A0-A7 is controlled by AEN and is not necessary, but may be
used to drive a heavily loaded system address bus during
transfers. The data bus transceivers simply isolate the DMA
controller from the local microprocessor bus and allow
programming on the upper or lower half of the data bus.
TRANSCEIVER
DACK 0-3
LATCH
A0-A7
MEMW
MEMR
AEN
IOW
T/R
IOR
TRANSCEIVER
A0 - A23
D0 - D15
SYSTEM
OE
BUS
IOR
IOW
MEMR
MEMW
TO CORRESPONDING
82C288 SIGNALS AND
MEMORY/PERIPHERALS
MEMORY
DEVICE
I/O
DREQ
CS
March 20, 2006
MEMR
MEMW
MEMCS
IOR
IOW
DACK
FN2967.2