M66291GP#201 Renesas Electronics America, M66291GP#201 Datasheet - Page 85
M66291GP#201
Manufacturer Part Number
M66291GP#201
Description
IC USB CONTROLLER GEN-PUR 48LQFP
Manufacturer
Renesas Electronics America
Datasheet
1.M66291GP201.pdf
(126 pages)
Specifications of M66291GP#201
Package / Case
48-LQFP
Mounting Type
Surface Mount
Current - Supply
30mA
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-20°C ~ 85°C
Interface
Serial
Controller Type
USB 2.0 Controller
Lead Free Status / RoHS Status
Not Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
M 6 6 2 9 1 G P / H P
R e v 1 . 0 1
(2) Buffer state and IVAL bit of the IN buffer
The relation between buffer state and IVAL bit is shown in Figure 3.3 when the buffer is set to IN (set by the
EPi_DIR bit/ISEL bit).
The single/double buffer mode is set by the EPi_DBLB bit. The double buffer mode cannot be set at endpoint 0.
2 0 0 4 . 1 1 . 0 1
W hen set to IN buffer
Figure 3.3 Relation between Buffer State and IVAL Bit (when set to IN buffer)
Response (Note1)
<W hen set to single buffer mode>
<W hen set to double buffer mode >
Response (Note 1)
Transmits data
Transmits data
Transmits data
Transmits data
Transmits data
Transmits data
Note 1. Response to the host when EP0_PID/EPn_PID bits are set to "01(BUF)".
Note 2. About the transmit/write completions, refer to the follows:
p a g e 8 5 o f 1 2 2
Endpoint 0
O thers endpoint 0
NAK
NAK
NAK
NAK
NAK
NAK
NAK
NAK
NAK
NAK
CTRR bit of Control Transfer Control Register
EPnRW MD bit of EPn Configuration Register
Transm it com pletion (Note 2)
SIE bus
SIE bus
Transm it com pletion (Note 2)
Transm it com pletion (Note 2)
SIE side buffer
SIE side buffer
Transmit data
Transmit data
Transmit data
Transmit
Transmit
Transmit
data
data
data
Empty
Empty
Empty
Empty
Empty
Empty
CPU side buffer
Write com pletion (Note 2)
Write com pletion (Note 2)
Transmit data
CPU side buffer
Transmit data
Transmit data
Write com pletion (Note 2)
Empty
Empty
Empty
Empty
Empty
Empty
Empty
Transmit
Transmit
Transmit
data
data
data
CPU bus
CPU bus
IVAL bit ="0"
IVAL bit ="0"
IVAL bit ="1"
IVAL bit ="1"
IVAL bit ="1"
IVAL bit ="1"
IVAL bit ="0"
(EPB_RDY bit is set to "1")
IVAL bit ="0"
IVAL bit ="0"
IVAL bit ="1"
IVAL bit ="0"
(EPB_RDY bit is set to "1")
IVAL bit ="0"
IVAL bit ="1"
IVAL bit ="0"
(EPB_RDY bit is set to "1")
IVAL bit ="0"
IVAL bit ="0"
Accessable
Not accessable