CY7C66013-PVC Cypress Semiconductor Corp, CY7C66013-PVC Datasheet - Page 19

• Manufacturer Part Number: CY7C66013-PVC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66013-PVC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

9.0
The CY7C66111/12/13 features a Digital to Analog Conversion (DAC) port which has programmable current sink on each I/O pin.
Writing a ‘1’ to a DAC I/O pin disables the output current sink (Isink DAC) and drives the I/O pin HIGH through an integrated 14-k
resistor. When a ‘0’ is written to a DAC I/O pin, the Isink DAC is enabled and the pull-up resistor is disabled. A ‘0’ output will cause
the Isink DAC to sink current to drive the output LOW. The amount of sink current for the DAC I/O pin is programmable over 16
values based on the contents of the DAC Isink Register for that output pin. DAC[1:0] are high current outputs that are program-
mable from a minimum of 3.2 mA to a maximum of 16 mA (typical). DAC[7:2] are low current outputs that are programmable from
a minimum of 0.2 mA to a maximum of 1.0 mA (typical).
When a DAC I/O bit is written as a ‘1’, the I/O pin is either an output pulled HIGH through the 14-k
internal 14-k
9.1
A DAC port interrupt can be enabled/disabled for each pin individually. The DAC Port Interrupt Enable register provides this feature
with an interrupt mask bit for each DAC I/O pin. Writing a ‘1’ to a bit in this register enables interrupts from the corresponding bit
position. Writing a ‘0’ to a bit in the DAC Port Interrupt Enable register disables interrupts from the corresponding bit position. All
of the DAC Port Interrupt Enable register bits are cleared to ‘0’ during a reset.
not used
DAC[7]
P1[7]
P2[7]
DAC Port Interrupts
DAC Port
pull-up resistor. All DAC port data bits are set to ‘1’ during reset.
Internal
Data Bus
DAC[6]
P1[6]
P2[6]
P3[6]
Interrupt
Enable
Interrupt
Polarity
Internal
Buffer
0.2 mA to 1.0 mA typical
Figure 8-10. Port 3 Interrupt Enable 0x07 (read/write)
Figure 8-8. Port 1 Interrupt Enable 0x05 (read/write)
Figure 8-9. Port 2 Interrupt Enable 0x06 (read/write)
DAC[5]
P1[5]
P2[5]
P3[5]
Low current outputs
DAC Write
DAC Read
Data
Out
Latch
PRELIMINARY
Figure 9-2. DAC Port Data 0x30 (read/write)
Figure 9-1. Block Diagram of a DAC Pin
Isink
Register
DAC[4]
P1[4]
P2[4]
P3[4]
4 bits
19
Isink
DAC
to Interrupt
Controller
DAC[3]
P1[3]
P2[3]
P3[3]
V
CC
Q1
14 k
DAC[2]
P1[2]
P2[2]
P3[2]
DAC
I/O Pin
CY7C66011/12/13
CY7C66111/12/13
3.2 mA to 16 mA typical
DAC[1]
resistor or an input with an
P1[1]
P2[1]
P3[1]
High current outputs
DAC[0]
P1[0]
P2[0]
P3[0]