CY7C66013-PVC Cypress Semiconductor Corp, CY7C66013-PVC Datasheet - Page 31

• Manufacturer Part Number: CY7C66013-PVC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66013-PVC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

Bits[7:5] in the endpoint 0 mode registers (EPA0 and EPB0) are “sticky” status bits that are set by the SIE to report the type of
token that was most recently received by the corresponding device address. The sticky bits must be cleared by firmware as part
of the USB processing.
The ‘ACK’ bit is set whenever the SIE engages in a transaction that completes with an ‘ACK’ packet.
The ‘SETUP’ PID status (bit 7) is forced HIGH from the start of the data packet phase of the SETUP transaction, until the start
of the ACK packet returned by the SIE. The CPU is prevented from clearing this bit during this interval, and subsequently until
the CPU first does a IORD to this endpoint 0 mode register.
Bits[6:0] of the endpoint 0 mode register are locked from CPU IOWR operations only if the SIE has updated one of these bits,
which the SIE does only at the end of a packet transaction (SETUP ... Data... ACK, or OUT... Data... ACK, or IN... Data... ACK).
The CPU can unlock these bits by doing a subsequent I/O read of this register.
Firmware must do a IORD after an IOWR to an endpoint 0 register to verify that the contents have changed and that the SIE has
not updated these values.
While the ‘SETUP’ bit is set, the CPU cannot write to the endpoint zero DMA buffers. This prevents an incoming SETUP trans-
action from conflicting with a previous In data buffer filling operation by firmware. Reference Table 18-1 for the appropriate endpoint
zero memory locations.
The mode bits (bits [3:0]) in an Endpoint Mode Register control how the endpoint responds to USB bus traffic. The mode bit
encoding is shown in Table 19-1 . Additional information on the mode bits can be found in Table 19-2 and Table 19-3 .
The mode bits (bits [3:0]) of the Endpoint Mode Register control how the endpoint responds to USB bus traffic. The mode bit
encoding is shown in Table 19-1 . If STALL bit (bit 7), the SIE will stall an OUT packet if the mode bits are set to ACK-IN, and the
SIE will stall an IN packet if the mode bits are set to ACK-OUT. For all other modes the STALL bit must be a LOW. For non-zero
endpoints, bits [6:5] are reserved.
The format of the endpoint Device counter registers is shown below:
Bits 0 to 5 indicate the number of data bytes to be transmitted during an IN packet, valid values are 0 to 32 inclusive. Data Valid
bit 6 is used for OUT and SETUP tokens only. Data 0/1 Toggle bit 7 selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1.
Endpoint 0
Received
Data 0/1
SETUP
STALL
Toggle
Figure 18-3. USB Non-Control Device Endpoint Mode Registers 0x14, 0x16, 0x44, (read/write)
Endpoint 0
Figure 18-4. USB Device Counter Registers 0x11, 0x13, 0x15, 0x41, 0x43 (read/write)
Data Valid
Figure 18-2. USB Device Endpoint Zero Mode Registers 0x12 and 0x42, (read/write)
Received
Not Used
IN
Byte Count
Endpoint 0
Received
Not Used
OUT
Bit 5
PRELIMINARY
Byte Count
ACK
ACK
Bit 4
31
Byte Count
Mode
Mode
Bit 3
Bit 3
Bit 3
Byte Count
Mode
Mode
Bit 2
Bit 2
Bit 2
Byte Count
CY7C66011/12/13
CY7C66111/12/13
Mode
Mode
Bit 1
Bit 1
Bit 1
Byte Count
Mode
Mode
Bit 0
Bit 0
Bit 0