CY7C66013-PVC Cypress Semiconductor Corp, CY7C66013-PVC Datasheet - Page 22

• Manufacturer Part Number: CY7C66013-PVC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66013-PVC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

Table 11-2. I
12.0
The I
located at I/O address 0x28. The data register is located at I/O address 0x29 and is implemented as separate read and write
registers. The bit definition and functionality for the HAPI/I
Note that once the I
of the corresponding port will be placed in the Open Drain mode, regardless of the settings of the GPIO Configuration Register
(0x08).
The I
1 or GPIO port 2. The port selection is determined by settings in the register 0x09, HAPI/I
The control/status bits are defined as follows:
MSTR Mode: This bit causes the I
the I
will result in the clearing of this bit, the setting of the ARB Lost bit, and the generation of an interrupt to the microcontroller. If the
chip is target of an external master then the interrupt will be held off until the transaction from the external master is completed.
Continue / Busy: This bit is written by the firmware to indicate that the firmware has responded to an interrupt request and has
completed the required update/read of the data register. On a read this bit indicates if the hardware is busy and can not accep t
additional writes to the I
one (1). Whenever this bit is set the hardware inhibits writes to the control register. This is to allow for the hardware to complete
certain operations that may require an extended period of time. This bit will not be set following an interrupt until the Continue bit
is set. This allows the firmware to make one write to the control register without the need to check the Busy bit.
Xmit Mode: When the I
Continue bit. The firmware will determine the value of this bit by looking at the R/W bit of the address received as a slave or
directly set it when sending as a master.
ACK: This bit is set or cleared by the firmware during receive operation to indicate if the hardware should generate an ACK signal
on the I
inversion is present since the ACK signal on the I
Addr: This bit is set by the I
Continue bit after reading the byte. The Xmit bit must be set according to the R/W bit of the address. The primary purpose of this
bit is to allow the firmware to recognize when the master has lost arbitration. Since the chip may be the target of the external
master the firmware needs to recognize the difference between an interrupt due to the chip receiving an address byte and the
chip completing the send of an address.
ARB Lost/Restart: This bit is valid as a status bit (ARB Lost) only after a MSTR Mode transaction has been attempted. See the
description of the MSTR Mode bit above. If during a master mode transaction the user wishes to perform an I
then this bit can be set, along with Continue and MSTR Mode, after the last data byte is sent. The I
written to the data register prior to setting the Continue bit as the Continue bit will cause the hardware to immediately begin the
restart sequence and transmission of the data register contents. To prevent false ARB Lost signals, the Restart bit is cleared by
hardware during the restart sequence.
MSTR
2
Mode
2
2
Bit 7
R/W
C bus as the target address. The I
C SCLK is connected to bit 0 of either GPIO port 1 or GPIO port 2. The I
C interface consists of two registers, a control and status register, and a data register. The status and control register is
7
I
2
2
C bus. This bit is written with the inverse value of the ACK bit from the I
C Position Bit
I
2
C Master Mode Controller
2
C Port Configuration
X
0
1
Continue/
2
C functionality is enabled by setting the bit 0 of the I
Busy
Bit 6
R/W
6
2
2
C needs to perform a transmit of data to an external master or slave this bit is set in conjunction with the
C control register. This bit is set following a write to the control register that sets the Continue bit to a
2
C during the first byte of a slave receive transaction. This bit is cleared when the firmware sets the
2
C to initiate a master mode transaction. The contents of the data register are transmitted on
Mode
Figure 12-1. I
Xmit
Bit 5
R/W
Port Width Bit[1]
5
2
PRELIMINARY
C block performs required arbitration and clock synchronization. The loss of arbitration
Figure 12-2. I
1
0
0
2
C bus is true LOW, this bit is true when HIGH (1).
2
C Status & Control 0x28 (read/write)
ACK
Bit 4
R/W
4
2
2
C Data 0x29 (read/write)
C Configuration Register (0x09) are explained in Section 11.0.
22
I
I
I
2
2
2
C on P2[1:0], 0:SCL, 1:SDA
C on P1[1:0], 0:SCL, 1:SDA
C on P2[1:0], 0:SCL, 1:SDA
Addr
Bit 3
R/W
3
I
2
2
C Status & Control Register to a HIGH, the LS 2 bits
C Position
2
C SDATA is connected to bit 1 of either GPIO port
2
C bus at the end of a transmit operation. The
ARB Lost/
Restart
Bit 2
R/W
2
2
C Configuration register.
Received Stop
CY7C66011/12/13
CY7C66111/12/13
2
Bit 1
R/W
C target address must be
1
2
C restart sequence
Enable
R/W
Bit 0
I
2
0
C