CY7C66013-PVC Cypress Semiconductor Corp, CY7C66013-PVC Datasheet - Page 26

• Manufacturer Part Number: CY7C66013-PVC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66013-PVC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

If one DAC pin has triggered an interrupt, no other DAC pins can cause a DAC interrupt until that pin has returned to its inactive
(non-trigger) state or the corresponding interrupt enable bit is cleared. The USB Controller does not assign interrupt priority to
different DAC pins and the DAC Interrupt Enable Register is not cleared during the interrupt acknowledge process.
15.8
Each of the GPIO pins can generate an interrupt, if enabled. The interrupt polarity can be programmed for each GPIO port as
part of the GPIO configuration. All of the GPIO pins share a single interrupt vector, which means the firmware will need to read
the GPIO ports with enabled interrupts to determine which pin or pins caused an interrupt.
If one port pin has triggered an interrupt, no other port pins can cause a GPIO interrupt until that port pin has returned to its
inactive (non-trigger) state or its corresponding port interrupt enable bit is cleared. The USB Controller does not assign interrupt
priority to different port pins and the Port Interrupt Enable Registers are not cleared during the interrupt acknowledge process.
When HAPI is enabled, the HAPI logic takes over the interrupt vector and blocks any interrupt from the GPIO bits, including
ports/bits not being used by HAPI. Operation of the HAPI interrupt is independent of the GPIO specific bit interrupt enables, and
is enabled or disabled only by bit 5 of the Global Interrupt Enable Register (0x20) when HAPI is enabled.The settings of the GPIO
bit interrupt enables on ports/bits not used by HAPI will still effect the CMOS mode operation of those ports/bits. The effect of
modifying the interrupt bits while the Port Config bits are set to “10” is shown in Table 8-1 .
15.9
The I
that the contents of the I
may change during I
interrupt to perform any writes to the Control Register as certain actions are taken when an interrupt is generated that may again
change the value of the Control Register and overwrite the data written there by the firmware. When enabled, the I
machines will generate interrupts on the following conditions:
The Continue bit is cleared prior to interrupt conditions 1 to 4 and the state machines require that this bit be set by the microcon-
troller to acknowledge the interrupt condition and indicate that the data register and status/control bits have been properly set up
for the state machine to continue.
Following an interrupt from the master mode controller the firmware may perform only one write to the control register 0x28 that
sets the Continue bit (register 0x28, bit 6, write) without checking the value of the Busy bit (register 0x28, bit 6, read). Following
the first write that sets the Continue bit, the hardware may engage a write inhibit function for a short period of time.
16.0
The USB hardware includes a USB Hub repeater with one upstream and four downstream ports. The USB Hub repeater interfaces
to the microcontroller through a high-speed serial interface engine (SIE). An external series resistor of R
placed in series with all the upstream and downstream USB outputs in order to meet the USB driver requirement, as defined by
the USB specification. The CY7C66xxx microcontroller can provide the functionality of a compound device consisting of a USB
hub and permanently attached functions.
1. When the slave receives a byte of data and the master is either inactive or has lost arbitration. The address bit will be set if
2. When the slave is in receive mode and detects a stop bit indicating the end of a transaction the Received Stop bit will be set
3. When the slave transmits a byte of data. The Ack bit of the I
4. When the master sends a byte of data. The setting of the Master bit initiates the master address transmit so the microcontroller
5. When the master receives a byte of data. The microcontroller must set the Ack and Continue/Busy bits appropriately. Clearing
6. When the master loses arbitration. This condition clears the Master bit and sets the Arbitration Lost bit immediately and then
this is the first byte since the start or restart signal was sent by the external master. The microcontroller must write data into
the data register if necessary then set the Ack, Xmit, and Continue/Busy bits appropriately.
and an interrupt will be generated.
the byte acknowledged the byte. The microcontroller needs to write the next byte of data into the data register and then set
the Xmit and Continue/Busy bits as required.
must place the data (address of target) in the data register prior to setting the Master bit. When the transmit is done the Ack
bit will indicate if the external target acknowledged the address. The microcontroller must set the Xmit, Master, and Contin-
ue/Busy bits appropriately. Clearing the Master bit will cause the master state machine to issue a stop signal to the I
and return to the idle state.
the Master bit at the same time will cause the master state machine to issue a stop signal to the I
state.
waits for a stop signal on the I
2
C interrupt serves two purposes. First, it informs the system that the I
GPIO/HAPI Interrupt
I
2
USB Overview
C Interrupt
2
C transactions prior to the generation of an interrupt. When this happens the firmware must wait for the
2
C Control & Status Register (0x28) are valid and that the control bits may be written to. The control bits
2
C bus to generate the interrupt.
PRELIMINARY
2
C Control & Status register will indicate if the master that requested
26
2
C hardware requires attention. Second, it indicates
CY7C66011/12/13
CY7C66111/12/13
2
C bus and return to the idle
ext
=20
±5
2
2
must be
C state
C bus