CY7C66013-PVC Cypress Semiconductor Corp, CY7C66013-PVC Datasheet - Page 23

• Manufacturer Part Number: CY7C66013-PVC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C66013-PVC

• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Not Compliant

Receive Stop: This bit is set when the slave is in receive mode and detects a stop bit on the bus. This bit is the only method for
the firmware to determine that a slave receive transaction has been terminated by the external master. The Receive Stop bit will
not be set if the firmware terminates the I
would happen when the firmware sets the Continue bit and clears the ACK bit in the I
I
and routes the appropriate signals to and from the pins so that they can be connected to the I
The I
by the slave when in receive mode, and when arbitration is lost.
All control of the I
13.0
The CY7C66xxx processor will provide a hardware assisted parallel interface for bus widths of 8, 16, or 24 bits, to accommodate
data transfer with an external microcontroller or a similar device. The bit definition and functionality for the HAPI/I
Register (0x09) is explained in Section 11.0.
The following signals are provided on P2 to control the HAPI interface.
The control bits for selecting 8-, 16-, or 24-bit width are Register 0x09, bits 1 and 0.
When writing a 24-bit or a 16-bit value to be transferred out to the External Interface, Byte 0 (to Port0) should be written last, as
this will trigger the assertion of Data_Ready. Likewise, when reading a 24-bit or a 16-bit value from the External Interface, Byte
0 (from Port0) should be read last, as this will trigger the assertion of Latch_Empty.
Both STB and OE cause a GPIO Interrupt (Vector 11). Firmware should read bits [3:2] of the HAPI/I
see if the interrupt was caused by STB or OE.
The status bits will update with the same timing or sooner than the external pins. The interrupt will be held off till the end of the
external cycle.
14.0
The “Run” (bit 0) is manipulated by the HALT instruction. When Halt is executed, the processor clears the run bit and halts at the
end of the current instruction. The processor remains halted until an appropriate reset occurs (power-on or watchdog).
The “Single Step” (bit 1) is provided to support a hardware debugger. When single step is set, the processor will execute one
instruction and halt (clear the run bit).
The “Interrupt Mask” (bit 2) shows whether interrupts are enabled or disabled. The firmware has no direct control over this bit as
writing a zero or one to this bit position will have no effect on interrupts. A ‘0’ indicates that interrupts are masked and a ‘1’ indicates
that the interrupts are enabled. This bit is further gated with the bit settings of the Global Interrupt Enable Register (0x20) and
USB End Point Interrupt Enable Register (0x21). Instructions DI, EI, and RETI manipulate the internal hardware that controls the
state of the interrupt mask bit in the Processor Status and Control Register.
Writing a ‘1’ to “Suspend, wait for interrupt” (bit 3) will halt the processor and cause the microcontroller to enter the “suspend”
mode that significantly reduces power consumption. The program counter that is pushed onto the program stack by the interrupt
service routine will be the instruction after the one that wrote ‘1’ to bit 3 of the Processor Status and Control Register.
The “Power-On Reset” (bit 4) is only set to ‘1’ during a power-on reset. The firmware can check bits 4 and 6 in the reset handler
to determine whether a reset was caused by a power-on condition or a watchdog timeout.
2
P2[2]
P2[3]
P2[4]
P2[5]
P2[6]
C Enable: When this bit is cleared the GPIO pins are free to function as GPIOs. Setting this bit sets the pins in the proper mode
Pending
Pin
2
IRQ
C will generate an interrupt to the microcontroller at the end of each byte received or transmitted, when a stop bit is detected
R
7
Hardware Assisted Parallel Interface (HAPI)
Processor Status and Control Register
Latch_Empty
Data_Ready
STB
OE
CS
2
Watch Dog
C data and clock lines is performed by the chip.
Name
Reset
R/W
6
USB Bus Re-
Figure 14-1. Processor Status and Control Register 0xFF
set Interrupt
Out
Out
In
In
In
R/W
5
PRELIMINARY
Direct
2
C transaction by not acknowledging the previous byte transmitted on the I
Power-On
Reset
R/W
Selectable
Selectable
Lo-True
Lo-True
Lo-True
4
Polarity
23
Suspend, Wait
for Interrupt
R/W
3
Out Data ready for Ext. Interface
Latches incoming data
Output Enable—Ready for more Out Data
Chip Select (Gates /STB and /OE)
Ready for more In Data from Ext. Interface
Interrupt
Mask
2
C Status & Control Register (0x28).
R
2
2
C bus.
Description
Single Step
CY7C66011/12/13
CY7C66111/12/13
2
C Configuration register to
R/W
1
2
C Configuration
2
C bus. This
R/W
Run
0