ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 37

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 6.
ISP1161A1_4
Product data sheet
Observed items
HcBufferStatus register
Bit 2 (ATLBufferFull)
Bit 5 (ATLBufferDone)
USB Traffic on USB Bus
Run results of the C program example
9.5 HC operational model
Upon power-up, the HCD initializes all operational registers (32-bit). The
FSLargestDataPacket field (bits 30 to 16) of the HcFmInterval register (0DH to read, 8DH
to write) and the HcLSThreshold register (11H to read, 91H to write) determine the end of
the frame for full-speed and low-speed packets. By programming these fields, the
effective USB bus usage can be changed. Furthermore, the size of the ITL buffers
(HcITLBufferLength, 2AH to read, AAH to write) is programmed.
If a USB frame contains both ISO and AT packets, two interrupts will be generated per
frame.
One interrupt is issued concurrently with the SOF. This interrupt (bit ITLint is set in the
Hc PInterrupt register) triggers reading and writing of the ITL buffer by the
microprocessor, after which the interrupt is cleared by the microprocessor.
Next the programmable ATL Interrupt (bit ATLint is set in the Hc PInterrupt register) is
issued, which triggers reading and writing of the ATL buffer by the microprocessor, after
which the interrupt is cleared by the microprocessor. If the microprocessor cannot handle
the ISO interrupt before the next ISO interrupt, disrupted ISO traffic can result.
To be able to send more than one packet to the same Control or Bulk endpoint in the
same frame, the Active bit and the TotalBytes field are introduced (see
is cleared only if all data of the Proprietary Transfer Descriptor (PTD) has been transferred
or if a transaction at that endpoint contained a fatal error. If all PTDs of the ATL are
serviced, and the frame is not over yet, the HC starts looking for a PTD with bit Active still
set. If such a PTD is found and there is still enough time in this frame, another transaction
is started on the USB bus for this endpoint.
For ISO processing, the HCD also has to take care of the HcBufferStatus register (2CH,
read only) for the ITL buffer RAM operations. After the HCD writes ISO data into ITL buffer
RAM, the ITL0BufferFull or ITL1BufferFull bit (depending on whether it is ITL0 or ITL1) will
be set to logic 1.
After the HC processes the ISO data in the ITL buffer RAM, the corresponding
ITL0BufferDone or ITL1BufferDone bit will automatically be set to logic 1.
The HCD can clear the buffer status bits by a read of the ITL buffer RAM. This must be
done within the 1 ms frame from which ITL0BufferDone or ITL1BufferDone was set.
For example, the HCD writes ISO_A data into the ITL0 buffer in the first frame. This will
cause the HcBufferStatus register to show that the ITL0 buffer is full by setting
bit ITL0BufferFull to logic 1. At this stage, the HCD cannot write ISO data into the ITL0
buffer RAM again.
HC not initialized and not in
USBOperational state
1
0
No
Rev. 04 — 29 January 2009
…continued
HC initialized and in
USBOperational state
1
1
Yes
USB single-chip host and device controller
Comments
transfer completed
PTD data processed by HC
OUT packets can be seen
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
Table
5). Bit Active
36 of 140