ISP1161A1BD,118 STEricsson, ISP1161A1BD,118 Datasheet - Page 67

• Manufacturer Part Number: ISP1161A1BD,118
• Manufacturer: STEricsson

Specifications of ISP1161A1BD,118

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 40.
ISP1161A1_4
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
HcTransferCounter register: bit allocation
10.4.3 HcTransferCounter register (R/W: 22H/A2H)
15
7
Table 39.
This register holds the number of bytes of a PIO or DMA transfer. For a PIO transfer, the
number of bytes being read or written to the Isochronous Transfer List (ITL) or
Acknowledged Transfer List (ATL) buffer RAM must be written into this register. For a
DMA transfer, the number of bytes must be written into this register as well. However, for
this counter to be read into the DMA counter, the HCD must set bit 2 (DMACounterSelect)
of the HcDMAConfiguration register. The counter value for ATL must not be greater than
1000H, and for ITL it must not be greater than 800H. When the byte count of the data
transfer reaches this value, the HC will generate an internal EOT signal to set bit 2
(AllEOTInterrupt) of the Hc PInterrupt register, and also update the HcBufferStatus
register.
Code (Hex): 22 — read
Code (Hex): A2 — write
Table 41.
Bit
2
1
0
Bit
15 to 0
14
6
Symbol
DMACounterS
elect
ITL_ATL_
DataSelect
DMARead
WriteSelect
HcDMAConfiguration register: bit description
HcTransferCounter register: bit description
Symbol
Counter
value
13
5
Rev. 04 — 29 January 2009
Description
0 — DMA counter not used. External EOT must be used
1 — Enables the DMA counter for DMA transfer. HcTransferCounter
register must be filled with non-zero values for DREQ1 to be raised
after bit DMA Enable is set
0 — ITL buffer RAM selected for ITL data
1 — ATL buffer RAM selected for ATL data
0 — read from the HC FIFO buffer RAM
1 — write to the HC FIFO buffer RAM
Description
The number of data bytes to be read to or written from RAM.
12
4
Counter value
Counter value
R/W
R/W
00H
00H
USB single-chip host and device controller
11
3
…continued
10
2
ISP1161A1
© ST-NXP Wireless 2009. All rights reserved.
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