MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 1197

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

29.3.2.5
The FPROT register defines which Flash sectors are protected against program or erase operations.
All bits in the FPROT register are readable and writable with restrictions (see
Protection
During the reset sequence, the FPROT register is loaded from the Flash Configuration Field at global
address 0x7F_FF0D. To change the Flash protection that will be loaded during the reset sequence, the
upper sector of the Flash memory must be unprotected, then the Flash Protect/Security byte located as
described in
Trying to alter data in any protected area in the Flash memory will result in a protection violation error and
the PVIOL flag will be set in the FSTAT register. The mass erase of a Flash block is not possible if any of
the Flash sectors contained in the Flash block are protected.
Freescale Semiconductor
KEYACC
CBEIE
Reset
Field
CCIE
7
6
5
W
R
FPOPEN
Restrictions”) except for RNV[6] which is only readable.
Command Buffer Empty Interrupt Enable — The CBEIE bit enables an interrupt in case of an empty command
buffer in the Flash module.
0 Command buffer empty interrupt disabled.
1 An interrupt will be requested whenever the CBEIF flag (see
Command Complete Interrupt Enable — The CCIE bit enables an interrupt in case all commands have been
completed in the Flash module.
0 Command complete interrupt disabled.
1 An interrupt will be requested whenever the CCIF flag (see
Enable Security Key Writing
0 Flash writes are interpreted as the start of a command write sequence.
1 Writes to Flash array are interpreted as keys to open the backdoor. Reads of the Flash array return invalid
Table 29-1
Flash Protection Register (FPROT)
F
7
(FSTAT)”)
is set.
data.
= Unimplemented or Reserved
is set.
RNV6
must be reprogrammed.
F
6
Figure 29-8. Flash Protection Register (FPROT)
Table 29-8. FCNFG Field Descriptions
FPHDIS
MC9S12XDP512 Data Sheet, Rev. 2.21
F
5
F
4
Description
FPHS
Chapter 29 128 Kbyte Flash Module (S12XFTX128K1V1)
F
3
Section 29.3.2.6, “Flash Status Register
Section 29.3.2.6, “Flash Status Register
FPLDIS
F
2
Section 29.3.2.5.1, “Flash
F
1
FPLS
(FSTAT)”)
F
0
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