MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 140

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 4 Analog-to-Digital Converter (ATD10B16CV4) Block Description
4.3.2.6
This register selects the type of conversion sequence and the analog input channels sampled. Writes to this
register will abort current conversion sequence and start a new conversion sequence. If external trigger is
enabled (ETRIGE = 1) an initial write to ATDCTL5 is required to allow starting of a conversion sequence
which will then occur on each trigger event. Start of conversion means the beginning of the sampling
phase.
Read: Anytime
Write: Anytime
140
Reset
DSGN
SCAN
MULT
Field
DJM
W
7
6
5
4
R
DJM
ATD Control Register 5 (ATDCTL5)
0
7
Result Register Data Justification — This bit controls justification of conversion data in the result registers.
See
0 Left justified data in the result registers.
1 Right justified data in the result registers.
Result Register Data Signed or Unsigned Representation — This bit selects between signed and unsigned
conversion data representation in the result registers. Signed data is represented as 2’s complement. Signed
data is not available in right justification. See <st-bold>4.3.2.16 ATD Conversion Result Registers (ATDDRx)
for details.
0 Unsigned data representation in the result registers.
1 Signed data representation in the result registers.
Table 4-15
Table 4-16
signal range between 0 and 5.12 Volts.
Continuous Conversion Sequence Mode — This bit selects whether conversion sequences are performed
continuously or only once. If external trigger is enabled (ETRIGE=1) setting this bit has no effect, that means
each trigger event starts a single conversion sequence.
0 Single conversion sequence
1 Continuous conversion sequences (scan mode)
Multi-Channel Sample Mode — When MULT is 0, the ATD sequence controller samples only from the
specified analog input channel for an entire conversion sequence. The analog channel is selected by channel
selection code (control bits CD/CC/CB/CA located in ATDCTL5). When MULT is 1, the ATD sequence controller
samples across channels. The number of channels sampled is determined by the sequence length value (S8C,
S4C, S2C, S1C). The first analog channel examined is determined by channel selection code (CC, CB, CA
control bits); subsequent channels sampled in the sequence are determined by incrementing the channel
selection code or wrapping around to AN0 (channel 0.
0 Sample only one channel
1 Sample across several channels
Section 4.3.2.16, “ATD Conversion Result Registers (ATDDRx)”
summarizes the result data formats available and how they are set up using the control bits.
illustrates the difference between the signed and unsigned, left justified output codes for an input
DSGN
0
6
Figure 4-8. ATD Control Register 5 (ATDCTL5)
Table 4-14. ATDCTL5 Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
SCAN
0
5
MULT
0
4
Description
CD
0
3
for details.
CC
0
2
Freescale Semiconductor
CB
0
1
CA
0
0