MC9S12XDP512CAL Freescale, MC9S12XDP512CAL Datasheet - Page 668

• Manufacturer Part Number: MC9S12XDP512CAL
• Manufacturer: Freescale

Specifications of MC9S12XDP512CAL

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 91
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 2(16-chx10-bit)
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 112
• Package Type: LQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 18 Memory Mapping Control (S12XMMCV3)
The fixed 16K page from 0x4000–0x7FFF (when ROMHM = 0) is the page number 0xFD.
The reset value of 0xFE ensures that there is linear Flash space available between addresses 0x4000 and
0xFFFF out of reset.
The fixed 16K page from 0xC000-0xFFFF is the page number 0xFF.
18.3.2.9
Read: Anytime
Write: Anytime
668
Address: 0x011C
PIX[7:0]
Reset
RWPE
Field
Field
AVIE
AVIF
7–0
0
1
0
Program Page Index Bits 7–0 — These page index bits are used to select which of the 256 FLASH or ROM
array pages is to be accessed in the Program Page Window.
RAM Write Protection Enable — This bit enables the RAM write protection mechanism. When the RWPE bit
is cleared, there is no write protection and any memory location is writable by the CPU module and the XGATE
module. When the RWPE bit is set the write protection mechanism is enabled and write access of the CPU or
to the XGATE RAM region. Write access performed by the XGATE module to outside of the XGATE RAM region
or the shared region is suppressed as well in this case.
0 RAM write protection check is disabled, region boundary registers can be written.
1 RAM write protection check is enabled, region boundary registers cannot be written.
CPU Access Violation Interrupt Enable — This bit enables the Access Violation Interrupt. If AVIE is set and
AVIF is set, an interrupt is generated.
0 CPU Access Violation Interrupt Disabled.
1 CPU Access Violation Interrupt Enabled.
CPU Access Violation Interrupt Flag — When set, this bit indicates that the CPU has tried to write a memory
location inside the XGATE RAM region. This flag can be reset by writing ’1’ to the AVIF bit location.
0 No access violation by the CPU was detected.
1 Access violation by the CPU was detected.
RAM Write Protection Control Register (RAMWPC)
0
7
= Unimplemented or Reserved
Figure 18-17. RAM Write Protection Control Register (RAMWPC)
0
6
Table 18-15. RAMWPC Field Descriptions
Table 18-14. PPAGE Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
0
4
Description
Description
0
3
0
2
Freescale Semiconductor
0
1
0
0