LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 108

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

6-8
STS
BER
LRB/AD0
AAS
LAB
BB_N
Two-Wire Serial Registers
Slave Mode Stop
This bit is set if the STOP condition is detected when the
LSI53C040 is in slave receive mode.
Bus Error Detection
This bit is set if a bus error is detected by the LSI53C040,
(i.e., Misplaced Start or Stop). Setting this bit clears the
BB_N bit and resets the PIN bit.
Last Received Bit/Address 0 Bit
This bit specifies one of the following, depending on the
state of the protocol when this bit is set (for more
information, refer to
Addressed as Slave
When active (1), this bit signifies that an address was
received across the two-wire data register interface that
matches the programmed
= 000)
cleared, the address matches the general call address.
Lost Arbitration Bit
In a multiple master environment, if the LSI53C040 loses
arbitration to another master on the bus, then it will
relinquish control to the other master and set this bit. It
should be noted that if two masters are simultaneously
active on the Data register interface requesting the exact
same operation, then the two masters will not observe
each other and a parallel operation has occurred.
Bus Busy
When active (logic 0), this active low bit signifies that the
Data register interface is currently in use and access is
not possible. It is activated upon detection of a start
condition and deactivated upon detection of a stop
condition.
If the slave selection address was the preprogrammed
Own Address register value (logic 0) or the General
Call address (logic 1) during Slave Selection
operation, this bit indicates a read (1) or write (0)
request.
The last bit received during data transfer. Useful for
testing ACK reception from a slave device.
register (0xFD00/0xFD02) setting. When this bit is
Figure
Own Address (ES0, ES1, ES2
2.11,
page
2-19).
5
4
3
2
1
0