LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 31

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.4 DMA Function
The LSI53C040 DMA function is designed to automatically handshake
with the SCSI core for SCSI send and receive operations. For SCSI send
operations, the DMA reads a byte from memory and writes it to the SCSI
core when requested. For receive operations, the DMA receives a byte
from the SCSI core and writes it to memory.
After setting up the transfer length and source/destination addresses, a
DMA operation begins with the microcontroller setting the TIP bit in the
DMA Status (DS)
of the microcontroller core to place the core into idle mode while the
DMA waits for the microcontroller to halt. With the microcontroller halted,
the DMA has control of the internal bus. For a send, the DMA first reads
a byte of data from internal or external memory. After each byte transfer,
the
address register incremented.
This cycle repeats until the transfer length is zero, which indicates the
last byte is being transferred.
A DMA receive operation happens in much the same way. This data byte
is written to the memory address pointed to by the DMA address
registers. Finally, the
and the address pointer register is incremented.
This cycle repeats until the transfer length is zero. This indicates the last
byte is being transferred.
If any interrupt not masked in the
generated during a DMA transfer, the microcontroller will come out of idle
mode and the DMA transfer will be halted. The DMA address pointer and
transfer length registers will not be cleared, so that the microcontroller
can determine at what point the transfer was interrupted.
During DMA transfers, the DMA block controls the internal bus and the
pins that bring these signals out to external memory. External memory
accesses function as illustrated in
DMA Function
DMA Transfer Length (DTL)
Note:
The entire address, which is a combination of two byte-
wide registers, will be incremented.
register. Next, the firmware sets bit 1 in register 0x87
DMA Transfer Length (DTL)
register will be decremented and the
Interrupt Mask (IMR)
Figure
2.7.
register is decremented
register is
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