LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 46

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 2.5
2.10.1.1 Interrupt Status Register (0xFE04)
2-28
Register Bit
Location
0xFE04
0xFE0D
0xFE0E
0xFC05, bit 7
0xFC02, bit 4
0xFC02, bit 2
0xFC07 (Read
register)
0xFC10, bit 1
0xFC14, bit 0
Register Bits for Interrupt Handling
Register or Bit
Name
Interrupt Status
Interrupt Mask
Interrupt
Destination
End of DMA
Transfer
Enable Parity
Interrupt
Monitor Busy
Reset
Parity/Interrupt
Register
DMA Interrupt
Enable
DMA Interrupt
The bits in this register are set when the corresponding interrupt
condition occurs. They are cleared when the interrupt is cleared by the
microcontroller. The register contains interrupt bits for the two SFF-8067
ports or MPIO3_[1:0]; the two programmable timers; the DMA core; the
Two-Wire Serial interfaces; and the SCSI core.
Functional Description
Function
Reports to the microcontroller which block asserted the interrupt.
Individual bits in this register may be written to force an interrupt
on the corresponding bit. Refer to the register description for
complete information.
Clearing individual bits in this register masks the corresponding
interrupts in the
to the microcontroller.
The bits in this register can be set or cleared to route interrupts
to either of the two interrupt sources to the microcontroller core.
This bit is set when the DMA transfer is complete.
When set, causes an interrupt from the SCSI core to occur if a
parity error is detected. The Enable Parity Checking bit must
also be set.
When set, causes an interrupt from the SCSI core to be
generated for an unexpected loss of BSY/.
Any read to this register resets the Interrupt Request Active bit
(0xFC05, bit 4).
When set, the DMA function will generate an interrupt whenever
the TIP bit (bit 0) transitions from 1 to 0. This signifies that the
transfer completed normally, or was interrupted.
This is the interrupt value for the DMA function. This interrupt will
only be enabled if the IEN bit (bit 1 in register 0xFC10) is set.
Interrupt Status (ISR)
register from being sent