LSI53C040-160QFP LSI, LSI53C040-160QFP Datasheet - Page 34

• Manufacturer Part Number: LSI53C040-160QFP
• Manufacturer: LSI

Specifications of LSI53C040-160QFP

• Mounting: Surface Mount
• Lead Free Status / RoHS Status: Supplier Unconfirmed

2.6.1 Two-Wire Serial Interface Transfer Rate
2.6.2 Power-On Serial ROM Download
2-16
The Two-Wire Serial interface performs all initial downloads at a
78.125 kHz SCL clock rate (with a 40 MHz system clock). At 78.125 kHz,
an entire 64 Kbit (8 Kbit x 8) serial EEPROM device can be downloaded
in under 945 ms. Other SCL clock rates can be achieved by
programming the
(0xFD00/0xFD02). See
register in the Two-Wire Serial register block.
At power-on, the Two-Wire Serial interface in the LSI53C040 attempts to
read from a serial EEPROM with slave address 0b1010, and a chip
address defined at power-on through the use of external pull-up/pull-
down options on signal pins A10, A9, and A8. These options are
summarized in
skipped if no pull-up resistor is used on signal pin AD5. Signal pin A11
indicates which serial interface will perform the initial download if the AD5
signal is high. A low on pin A11 indicates the download will occur through
serial port 0 while a high indicates the download will occur through serial
port 1. If an initial serial ROM download is attempted, the microcontroller
core will be delayed in fetching its first instruction until the download has
completed, so that firmware downloaded from the serial ROM can be
executed first if desired.
download to the LSI53C040.
sequence. The device ID to download from is 1010abc. The 0b1010
denotes a ROM device, and the “abc” value is the serial ROM chip
address, determined by the configuration of the A[10:8] pins as
presented in
Functional Description
Table
Table
Clock (ES0, ES1, ES2 = 010)
2.4.
2.4. The initial download attempt can also be
Chapter 6
Table 2.1
Figure 2.10
for more information on the Clock
lists the contents of the initial ROM
illustrates a typical download
register