PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 113

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Table 7-1. EVO unit interface pins
7.6
Figure 7-4
sists of a clock generator, a video frame timing generator
and an image or data generator. The image generator
produces either a CCIR 656 digital video data stream
with optional YUV overlay or a continuous-data or mes-
sage-data stream. It also performs optional format con-
version and optional 2:1 horizontal scaling.
Figure 7-3. EVO unit connected to the VI unit of a
second PNX1300.
VO_DATA[7:0
Signal Name
VO_CLK
VO_IO1
VO_IO2
(ENDMSG) VO_IO2
]
PNX1300 A
(STMSG) VO_IO1
BLOCK DIAGRAM
VO_DATA[7:0]
shows a block diagram of the EVO unit. It con-
VO_CLK
I/O-5 Horizontal Sync (HS) output or Start
I/O-5 Frame Sync (FS) input, FS output or
I/O-5 The EVO unit emits VO_DATA on a
OUT CCIR 656-style YUV 4:2:2 digital out-
Typ
e
put data, or general-purpose high
speed data output channel. Output
changes on positive edge of VO_CLK.
Message (STMSG) output. See
Figure
ENDMSG output.
• If set as FS input, it can be set to
• If the EVO operates in Genlock mode
• In message-passing mode, this pin
positive edge of VO_CLK. VO_CLK
can be configured as an input (the
hardware reset default) or output.
• If configured as an input, VO_CLK is
• If configured as output, the PNX1300
respond to positive or negative edge
transitions.
and the selected transition occurs,
the EVO sends two fields of video
data.
acts as the ENDMSG output. See
Figure
received from external display-clock
master circuitry.
emits a low-jitter clock frequency
programmable between approx. 4
and 81 MHz.
logic ‘1’
7-18.
7-18.
Description
VI_DATA[7:0]
VI_DATA[8]
VI_DATA[9]
VI_CLK
VI_DVALID
PNX1300 B
The frame timing generator provides programmable im-
age timing including horizontal and vertical blanking,
SAV and EAV code insertion, overlay start and end tim-
ing, and horizontal and frame timing pulses. It also sup-
plies data-valid timing signals in data-streaming mode
and start-of-message and end-of-message timing sig-
nals in message-passing mode. The sync timing pulses
can be generated by the frame timing unit, or the frame
timing unit can be driven by externally-supplied sync tim-
ing pulses, when VO_CTL. SYNC_MASTER = 0 and
EVO_CTL. GENLOCK = 1.
The video clock generator produces a programmable
video clock. The video clock generator can supply the
video clock for the frame timing generator and external
devices, or it can be driven by an external clock signal.
7.7
Positive edges of VO_CLK drive all EVO output events.
A block diagram of the EVO clock system is shown in
Figure
internally generated by the EVO, as controlled by the
VO_CTL. CLKOUT bit. When CLKOUT = 0, the EVO
clock is supplied by an external source through the
VO_CLK pin as an input. This is the default mode, en-
tered at hardware reset. When CLKOUT = 1, an internal
clock generator supplies the EVO clock and drives the
VO_CLK pin as an output.
The internal clock generator system is a square wave Di-
rect Digital Synthesizer (DDS) which can be pro-
grammed to emit frequencies from 1 Hz to 50 MHz. The
output of the DDS is sent to a phase-locked loop filter
(PLL) which removes clock jitter from the DDS output
PRELIMINARY SPECIFICATION
Figure 7-4. EVO unit block diagram.
Figure 7-5. EVO clock system.
9 × CPU Clock
31
7-5. The EVO clock is either supplied externally or
Square-Wave DDS
CLOCK SYSTEM
Video Clock
Generator
Message/Data Generator
FREQUENCY
Overlay Generator
Image Generator
(to Frame Timing Gen.)
VO_CLK Internal
Video Frame
0
Generator
CLKOUT
Timing
Filter
PLL
Enhanced Video Out
VO_IO2
(VS, End Msg, or
valid data level)
VO_CLK
VO_IO1
(HS, Start Msg, or
valid data pulse)
VO_DATA[0:7]
VO_CLK
7-3