PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 337

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
fabsvalflags
SYNTAX
FUNCTION
DESCRIPTION
value of rsrc1 and writes a bit vector representing the exception flags into rdest. The argument value is in IEEE single-
precision floating-point format; the result is an integer bit vector. The bit vector stored in rdest has the same format as
the IEEE exception bits in the PCSW. The exception flags in PCSW are left unchanged by this operation. If rsrc1 is
denormalized, the IFZ bit in the result is set.
the modification of the destination register. If the LSB of rguard is 1, rdest is written; otherwise, rdest is not changed.
EXAMPLES
A-39
r30 = 0x40400000 (3.0)
r35 = 0xbf800000 (-1.0)
r40 = 0x00400000 (5.877471754e-39)
r45 = 0xffffffff (QNaN)
r50 = 0xffbfffff (SNaN)
r10 = 0,
r55 = 0xff7fffff (–3.402823466e+38)
r20 = 1,
r55 = 0xff7fffff (–3.402823466e+38)
The
The
[ IF rguard ] fabsvalflags rsrc1 → rdest
if rguard then
rdest ← ieee_flags(abs_val((float)rsrc1))
fabsvalflags
fabsvalflags
31
0
Initial Values
PRELIMINARY SPECIFICATION
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls
operation computes the IEEE exceptions that would result from computing the absolute
fabsvalflags r30 → r90
fabsvalflags r35 → r95
fabsvalflags r40 → r100
fabsvalflags r45 → r105
fabsvalflags r50 → r110
IF r10 fabsvalflags r55 → r115
IF r20 fabsvalflags r55 → r120
IEEE status flags from floating-point absolute
Operation
7
0
OFZ
6
IFZ
5
INV
4
fabsval faddflags readpcsw
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
r90 ← 0x0
r95 ← 0x0
r100 ← 0x20 (IFZ)
r105 ← 0x0
r110 ← 0x10 (INV)
no change, since guard is false
r120 ← 0x0
OVF
3
Philips Semiconductors
UNF
ATTRIBUTES
2
SEE ALSO
Result
INX
1
DBZ
0
value
1, 4
falu
116
No
—
1
3