PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 348

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

Philips Semiconductors
Floating-point compare less-than or equal
pseudo-op for fgeq
SYNTAX
FUNCTION
DESCRIPTION
exchanged (
source files.)
second argument, rsrc2; otherwise, rdest is set to 0. The arguments are treated as IEEE single-precision floating-point
values; the result is an integer. If an argument is denormalized, zero is substituted for the argument before computing
the comparison, and the IFZ flag in the PCSW is set. If
flags in the PCSW are set. The PCSW exception flags are sticky: the flags can be set as a side-effect of any floating-
point operation but can only be reset by an explicit
occurs at the same time as rdest is written. If any other floating-point compute operations update the PCSW at the
same time, the net result in each exception flag is the logical OR of all simultaneous updates ORed with the existing
PCSW value for that exception flag.
modification of the destination register. If the LSB of rguard is 1, rdest and the exception flags in PCSW are written;
otherwise, rdest is not changed and the operation does not affect the exception flags in PCSW.
EXAMPLES
r30 = 0x40400000 (3.0), r40 = 0 (0.0)
r30 = 0x40400000 (3.0)
r10 = 0, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r20 = 1, r60 = 0x3f800000 (1.0),
r30 = 0x40400000 (3.0)
r30 = 0x40400000 (3.0),
r60 = 0x3f800000 (1.0)
r30 = 0x40400000 (3.0),
r61 = 0xffffffff (QNaN)
r50 = 0x7f800000 (+INF)
r55 = 0xff800000 (-INF)
r60 = 0x3f800000 (1.0),
r65 = 0x00400000 (5.877471754e-39)
r50 = 0x7f800000 (+INF)
The
The
The
The
[ IF rguard ] fleq rsrc1 rsrc2 → rdest
if rguard then {
}
if (float)rsrc1 <= (float)rsrc2 then
else
fleq
fleqflags
fleq
fleq
rdest ← 1
rdest ← 0
Initial Values
fleq
operation sets the destination register, rdest, to 1 if the first argument, rsrc1, is less than or equal to the
operation optionally takes a guard, specified in rguard. If a guard is present, its LSB controls the
operation is a pseudo operation transformed by the scheduler into an
’s rsrc1 is
operation computes the exception flags that would result from an individual
fgeq
’s rsrc2 and vice versa). (Note: pseudo operations cannot be used in assembly
fleq r30 r40 → r80
fleq r30 r30 → r90
IF r10 fleq r60 r30 → r100
IF r20 fleq r60 r30 → r110
fleq r30 r60 → r120
fleq r30 r61 → r121
fleq r50 r55 → r125
fleq r60 r65 → r126
fleq r50 r50 → r127
writepcsw
Operation
fleq
PRELIMINARY SPECIFICATION
causes an IEEE exception, the corresponding exception
operation. The update of the PCSW exception flags
PNX1300/01/02/11 DSPCPU Operations
r80 ← 0
r90 ← 1
no change, since guard is false
r110 ← 1
r120 ← 0
r121 ← 0, INV flag set
r125 ← 0
r126 ← 0, IFZ flag set
r127 ← 1
Function unit
Operation code
Number of operands
Modifier
Modifier range
Latency
Issue slots
ileq fgeq fleqflags
readpcsw writepcsw
fgeq
ATTRIBUTES
SEE ALSO
Result
fleq
with the arguments
.
fcomp
fleq
146
No
—
2
1
3
A-50