PNX1311EH NXP Semiconductors, PNX1311EH Datasheet - Page 202

• Manufacturer Part Number: PNX1311EH
• Manufacturer: NXP Semiconductors

Specifications of PNX1311EH

• Lead Free Status / RoHS Status: Not Compliant

PNX1300/01/02/11 Data Book
13.2
The PNX1300 boot sequence begins with the assertion
of the reset signal TRI_RESET#. After reset is de-assert-
ed, only the system boot block, I
are allowed to operate. In particular, the DSPCPU and
the internal data highway bus will remain in the reset
state until they are explicitly released during the boot pro-
cedure. In autonomous boot, the system boot block is re-
sponsible for releasing the DSPCPU and highway from
reset. In host-assisted boot, the boot logic releases the
highway from reset and the PNX1300 software driver
(which runs on the host processor) releases the
DSPCPU from reset.
The system boot block operation is illustrated in a flow
chart shown in
13.2.1
There should be no other I
until boot EEPROM load completes. The system boot
procedure begins by loading a few critical pieces of infor-
mation from the serial EEPROM. This part of the proce-
dure is common to both autonomous and host-assisted
bootstrapping. See
Table 13-5
The first byte of the EEPROM is read using a serial clock
equal to BOOT_CLK/1000, which is guaranteed to be
less than 100 kHz. After reading the first byte, which con-
tains the actual BOOT_CLK rate as well as the EEPROM
speed capability, the boot block proceeds to read subse-
quent bytes at the highest valid speed.
The number of lines in the EEPROM device should be ‘0’
in case of a 128-byte device and ‘1’ for larger devices.
The SDRAM aperture size should be set to the smallest
size that is larger than or equal to the actual size of
SDRAM connected to PNX1300. The SDRAM aperture
size information is forwarded to the PCI interface for use
in host BIOS configuration, as described in
13.3.2, “Stage 2: Host-System PCI Configuration.”
The BOOT_CLK speed bits should be set to match the
closest rounded up frequency of the external clock cir-
cuit, i.e. for an external clock of 40 MHz or 50 MHz the
value should be 10. This field, together with the EE-
PROM maximum clock speed bit are used to decide the
best possible divider ratio for generation of the I
as shown in
Figure 13-2
BOOT_CLK value.
The EEPROM maximum clock speed bit is set to match
the speed grade of the serial EEPROM device.
The test mode bit should always be set to ‘0’. It is only set
to one for factory ATE testing.
The Subsystem ID and Subsystem Vendor ID data has
no meaning to the PNX1300 hardware; its meaning is
entirely software defined. The value is loaded by the sys-
13-2
BOOT HARDWARE OPERATION
Autonomous and Host-Assisted
Bootstrap
Boot Procedure Common to Both
for full bit-accurate EEPROM layout details.
Table
are
Figure
13-3. In addition, the delay actions in
taken
Table 13-2
13-2.
PRELIMINARY SPECIFICATION
2
based
C master active from reset
2
C, and PCI interfaces
for a summary and
on
the
2
specified
C clock,
Section
Table 13-2. Information Loaded During First Part of
Bootstrapping Procedure
tem boot block from the EEPROM and published in the
PCI configuration space register at offset 0x2C to pro-
vide the 16-bit Subsystem ID and Subsystem Vendor ID
values. These values are used by driver software to dis-
tinguish the board vendor and product revision informa-
tion for multiple board products based on the PNX1300
chip. Refer to
Number of lines in
EEPROM device
SDRAM aperture size
BOOT_CLK speed
I
Test mode
Subsystem ID
Subsystem Vendor ID
MM_CONFIG register
initialization
PLL_RATIOS register
initialization
Autonomous/host-
assisted boot
Enable internal
PCI_CLK
SDRAM prefetchable
2
C clock speed
Information
Section 11.5.12, “Subsystem ID, Sub-
16 bits
16 bits
20 bits
3 bits
2 bits
8 bits
Size
1 bit
1 bit
1 bit
1 bit
1 bit
1 bit
Philips Semiconductors
000 1 MB
001 1 MB
010 2 MB
100 8 MB
101 16 MB
Value is copied to Sub-
system ID register in PCI
configuration space.
Value is copied to Sub-
system Vendor ID regis-
ter in PCI config space.
Value is simply written to
the MM_CONFIG regis-
ter; see
“MM_CONFIG Register.”
Value is simply written to
the PLL_RATIOS regis-
ter; see
“PLL_RATIOS Register.”
011 4 MB
110 32 MB
111 64 MB
00
01
10
11
0
1
0
1
0
1
0
1
0
1
0
1
Interpretation
128 lines
256 or more lines
100 MHz
75 MHz
50 MHz
33 MHz
100 KHz
400 KHz
normal operation
rapid ATE testing
host-assisted
autonomous
PCI_CLK taken
from outside
use on-chip XIO
PCI_CLK clock
generator
Note: MUST be set
if no external PCI
clock is supplied
not prefetchable
prefetchable
Section 12.6.1,
Section 12.6.2,