GS816218BD-150I GSI TECHNOLOGY, GS816218BD-150I Datasheet

GS816218BD-150I

Manufacturer Part Number

GS816218BD-150I

Description

Manufacturer

GSI TECHNOLOGY

Datasheet

1.GS816218BD-150I.pdf (37 pages)

Specifications of GS816218BD-150I

Density

18Mb

Access Time (max)

7.5ns

Sync/async

Synchronous

Architecture

SDR

Clock Freq (max)

133.3MHz

Operating Supply Voltage (typ)

2.5/3.3V

Address Bus

20b

Package Type

FBGA

Operating Temp Range

-40C to 85C

Number Of Ports

Supply Current

185mA

Operating Supply Voltage (min)

2.3/3V

Operating Supply Voltage (max)

2.7/3.6V

Operating Temperature Classification

Industrial

Mounting

Surface Mount

Pin Count

165

Word Size

18b

Number Of Words

Lead Free Status / RoHS Status

Not Compliant

Current page: 1 of 37
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119-- & 165-Bump BGA

Commercial Temp

Industrial Temp

Features

• FT pin for user-configurable flow through or pipeline operation

• Single/Dual Cycle Deselect selectable

• IEEE 1149.1 JTAG-compatible Boundary Scan

• ZQ mode pin for user-selectable high/low output drive

• 2.5 V or 3.3 V +10%/–10% core power supply

• LBO pin for Linear or Interleaved Burst mode

• Internal input resistors on mode pins allow floating mode pins

• Default to SCD x18/x36 Interleaved Pipeline mode

• Byte Write (BW) and/or Global Write (GW) operation

• Internal self-timed write cycle

• Automatic power-down for portable applications

• JEDEC-standard 119-bump and 165-bump BGA packages

• RoHs-compliant 119-bump and 165-bump BGA packages available

Functional Description

Applications

The GS816218/36B(B/D) is an 18,874,368-bit high performance

synchronous SRAM with a 2-bit burst address counter. Although of a

type originally developed for Level 2 Cache applications supporting

high performance CPUs, the device now finds application in

synchronous SRAM applications, ranging from DSP main store to

networking chip set support.

Controls

Addresses, data I/Os, chip enable (E1), address burst control inputs

(ADSP, ADSC, ADV), and write control inputs (Bx, BW, GW) are

synchronous and are controlled by a positive-edge-triggered clock

input (CK). Output enable (G) and power down control (ZZ) are

asynchronous inputs. Burst cycles can be initiated with either ADSP

or ADSC inputs. In Burst mode, subsequent burst addresses are

generated internally and are controlled by ADV. The burst address

counter may be configured to count in either linear or interleave order

with the Linear Burst Order (LBO) input. The Burst function need not

be used. New addresses can be loaded on every cycle with no

degradation of chip performance.

Rev: 1.07 9/2008

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

Flow Through

Pipeline

3-1-1-1

2-1-1-1

18MbS/DCD Sync Burst SRAMs

Curr

1M x 18, 512K x 36

tCycle

Parameter Synopsis

(x18)

(x36)

(x18)

(x36)

1/37

Flow Through/Pipeline Reads

The function of the Data Output register can be controlled by the user

via the FT mode . Holding the FT mode pin low places the RAM in

Flow Through mode, causing output data to bypass the Data Output

activating the rising-edge-triggered Data Output Register.

SCD and DCD Pipelined Reads

The GS816218/36B(B/D) is an SCD (Single Cycle Deselect) and

DCD (Dual Cycle Deselect) pipelined synchronous SRAM. DCD

SRAMs pipeline disable commands to the same degree as read

commands. SCD SRAMs pipeline deselect commands one stage less

than read commands. SCD RAMs begin turning off their outputs

immediately after the deselect command has been captured in the

input registers. DCD RAMs hold the deselect command for one full

cycle and then begin turning off their outputs just after the second

rising edge of clock. The user may configure this SRAM for either

mode of operation using the SCD mode input.

Byte Write and Global Write

Byte write operation is performed by using Byte Write enable (BW)

input combined with one or more individual byte write signals (Bx).

In addition, Global Write (GW) is available for writing all bytes at one

time, regardless of the Byte Write control inputs.

FLXDrive™

The ZQ pin allows selection between high drive strength (ZQ low) for

multi-drop bus applications and normal drive strength (ZQ floating or

high) point-to-point applications. See the Output Driver

Characteristics chart for details.

Sleep Mode

Low power (Sleep mode) is attained through the assertion (High) of

the ZZ signal, or by stopping the clock (CK). Memory data is retained

during Sleep mode.

Core and Interface Voltages

The GS816218/36B(B/D) operates on a 2.5 V or 3.3 V power supply.

All input are 3.3 V and 2.5 V compatible. Separate output power

circuits and are 3.3 V and 2.5 V compatible.

-250

DDQ

295

345

225

255

2.5

4.0

5.5

) pins are used to decouple output noise from the internal

-200

245

285

200

220

3.0

5.0

6.5

-150

200

225

185

205

3.8

6.7

7.5

Unit

GS816218/36B(B/D)

250 MHz–150 MHz

2.5 V or 3.3 V V

2.5 V or 3.3 V I/O

Related parts for GS816218BD-150I

GS816218BD-150I Summary of contents

Page 1

... KQ tCycle 5.5 225 Curr (x18) 255 Curr (x36) 1/37 GS816218/36B(B/D) 250 MHz–150 MHz 3.3 V I/O -200 -150 Unit 3.0 3.8 ns 5.0 6.7 ns 245 200 mA 285 225 mA 6.5 7.5 ns 6.5 7.5 ns 200 185 mA 220 205 mA © 2004, GSI Technology DD ...

Page 2

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com ADSP DDQ ADSC DQP DDQ ADV DDQ SCD DDQ LBO TMS TDI TCK TDO DDQ 2/37 GS816218/36B(B/ DDQ DQP DDQ DDQ DDQ DQP DDQ © 2004, GSI Technology ...

Page 3

... Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com ADSP DDQ ADSC DDQ ADV DDQ SCD DDQ DQP LBO TMS TDI TCK TDO DDQ 3/37 GS816218/36B(B/ DDQ DQP DDQ DDQ DDQ DDQ © 2004, GSI Technology ...

Page 4

... SS A TDI A1 TDO A A TMS A0 TCK A 4/37 GS816218/36B(B/ ADV ADSP DQPA C DDQ V NC DQA D DDQ V NC DQA E DDQ V NC DQA F DDQ V NC DQA G DDQ DQA NC J DDQ V DQA NC K DDQ V DQA NC L DDQ V DQA NC M DDQ DDQ © 2004, GSI Technology ...

Page 5

... TDO A A TMS A0 TCK A 5/37 GS816218/36B(B/ ADV ADSP DQPB C DDQ V DQB DQB D DDQ V DQB DQB E DDQ V DQB DQB F DDQ V DQB DQB G DDQ DQA DQA J DDQ V DQA DQA K DDQ V DQA DQA L DDQ V DQA DQA M DDQ V NC DQPA N DDQ © 2004, GSI Technology ...

Page 6

... Single Cycle Deselect/Dual Cyle Deselect Mode Control Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock Core power supply I/O and Core Ground Output driver power supply Must connect low (165 BGA only) 6/37 GS816218/36B(B/D) I/Os; active low D © 2004, GSI Technology ...

Page 7

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. GS816218/36B Block Diagram Counter Load Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q Register D Q SCD 7/37 GS816218/36B(B/D) A Memory Array DQx1–DQx9 © 2004, GSI Technology ...

Page 8

... The burst counter wraps to initial state on the 5th clock. 8/37 GS816218/36B(B/D) Function Linear Burst Interleaved Burst Flow Through Pipeline Active Standby Dual Cycle Deselect Single Cycle Deselect High Drive (Low Impedance) Low Drive (High Impedance) A[1:0] A[1:0] A[1:0] A[1: BPR 1999.05.18 © 2004, GSI Technology ...

Page 9

... C D Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com may be used in any combination with BW to write single or multiple bytes. D 9/37 GS816218/36B(B/ Notes and/ © 2004, GSI Technology ...

Page 10

... Tying ADSP high and ADV low while using ADSC to load new addresses allows simple burst operations. See ITALIC items above. Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. State Diagram ADSP ADSC Key 10/37 GS816218/36B(B/D) ADV High High High High High © 2004, GSI Technology ...

Page 11

... ADSP is tied high and ADV is tied low. Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram X Deselect First Write Burst Write CR CW 11/37 GS816218/36B(B/ First Read Burst Read BW, and GW) control inputs, and © 2004, GSI Technology ...

Page 12

... Transitions shown in grey tone assume G has been pulsed high long enough to turn the RAM’s drivers off and for incoming data to meet Data Input Set Up Time. Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Simplified State Diagram with G X Deselect First Write Burst Write 12/37 GS816218/36B(B/ First Read Burst Read CR © 2004, GSI Technology ...

Page 13

... V maximum, with a pulse width not to exceed 50% tKC. DDn 13/37 GS816218/36B(B/D) Value –0.5 to 4.6 –0.5 to 4.6 –0 +0.5 DDQ –0 +0.5 DD +/–20 +/–20 1.5 –55 to 125 –55 to 125 Typ. Max. Unit 3.3 3.6 V 2.5 2.7 V 3.3 3.6 V 2.5 2.7 V © 2004, GSI Technology Unit Notes ...

Page 14

... A T – +1.5 V maximum, with a pulse width not to exceed 50% tKC. DDn 14/37 GS816218/36B(B/D) Max. Unit Notes 0.3 V 1,3 DDQ 0.8 V 1,3 Max. Unit Notes 0.3 0.3 V 1,3 DDQ 0.3*V V 1,3 DD Max. Unit Notes ° ° © 2004, GSI Technology ...

Page 15

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Overshoot Measurement and Timing Symbol Test conditions I/O OUT Conditions V – DDQ Fig. 1 Output Load 1 DQ 50Ω V DDQ/2 * Distributed Test Jig Capacitance 15/37 GS816218/36B(B/D) 50% tKC DD IL Typ. Max. Unit 30pF © 2004, GSI Technology ...

Page 16

... IN I Output Disable OUT –8 mA, V OH2 OH DDQ –8 mA, V OH3 OH DDQ 16/37 GS816218/36B(B/D) Min – ≥ V – ≤ V –1 uA 100 uA IH ≥ V –100 uA IL ≤ V – – 2.375 V 1 3.135 V 2.4 V — © 2004, GSI Technology Max — — 0.4 V ...

Page 17

... DD3 DD2 DDQ3 DDQ2 17/37 GS816218/36B(B/D) -200 -150 –40 0 –40 0 – 85°C 70°C 85°C 70°C 85°C 315 255 265 205 215 245 205 215 190 200 285 230 240 185 195 225 190 200 175 185 © 2004, GSI Technology Unit ...

Page 18

... GSI Technology ...

Page 19

... E2 and E3 only sampled with ADSP and ADSC tS tOHZ tH Q(A) D(B) 19/37 GS816218/36B(B/D) Read C+1 Read C+2 Read C+3 Cont Burst Read Burst Read Deselected with E1 E1 masks ADSP tKQ tLZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2004, GSI Technology Deselect tKQX tHZ ...

Page 20

... Cont Write B Read C Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read tKQ tOHZ tLZ D(B) Q(C) 20/37 GS816218/36B(B/D) Cont Deselect Deselected with E1 tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2004, GSI Technology tKQX ...

Page 21

... Read C+1 Read C+2 Read C+3 Cont tKL tKL tKH tKH tKC tKC ADSC initiated read and E3 only sampled with ADSC tS tKQ tOHZ tH tLZ Q(A) D(B) 21/37 GS816218/36B(B/D) Deselect Deselect Deselected with E1 tHZ Q(C) Q(C+1) Q(C+2) Q(C+3) © 2004, GSI Technology tKQX ...

Page 22

... Read C+1 Read C+2 Read C+3 Read C tKL tKL tKC tKC Fixed High tS tH ADSC initiated read masks ADSP E1 masks ADSP tH tS tOHZ tLZ Q(A) D(B) Q(C) 22/37 GS816218/36B(B/D) Deselect tH Deselected with E1 tKQX tHZ Q(C+1) Q(C+2) Q(C+3) Q(C) © 2004, GSI Technology ...

Page 23

... Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Sleep Mode Timing tKH tKH tKC tKC tKL tKL tZZS tZZH 23/37 GS816218/36B(B/D) 2. The duration of SB tZZR © 2004, GSI Technology ...

Page 24

... Boundary Scan Register also includes a number of place holder flip flops (always set to a logic 1). The relationship between the Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com TDO should be left unconnected Description 24/37 GS816218/36B(B/D) . The JTAG output DD © 2004, GSI Technology ...

Page 25

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. JTAG TAP Block Diagram · · · · · · Boundary Scan Register 0 Bypass Register Instruction Register ID Code Register · · · · Control Signals Test Access Port (TAP) Controller 25/37 GS816218/36B(B/D) · · TDO © 2004, GSI Technology ...

Page 26

... TAP executes newly loaded instructions only when the controller is moved to Update-IR state. The TAP instruction set for this device is listed in the following table. Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Not Used Configuration 26/37 GS816218/36B(B/D) GSI Technology I/O JEDEC Vendor ID Code © 2004, GSI Technology ...

Page 27

... Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. JTAG Tap Controller State Diagram 1 1 Select Capture DR 0 Shift Exit1 DR 0 Pause Exit2 Update 27/37 GS816218/36B(B/D) 1 Select Capture IR 0 Shift Exit1 IR 0 Pause Exit2 Update © 2004, GSI Technology ...

Page 28

... Z) and the Boundary Scan Register is connected between TDI and TDO when the TAP controller is moved to the Shift-DR state. RFU These instructions are Reserved for Future Use. In this device they replicate the BYPASS instruction. Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. 28/37 GS816218/36B(B/D) © 2004, GSI Technology ...

Page 29

... Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Conditions V – DDQ V /2 DDQ Description 29/37 GS816218/36B(B/D) JTAG Port AC Test Load 50Ω * 30pF V /2 DDQ * Distributed Test Jig Capacitance Notes © 2004, GSI Technology ...

Page 30

Page 31

... For information regarding the Boundary Scan Chain obtain BSDL files for this part, please contact our Applications Engineering Department at: apps@gsitechnology.com. Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. Min Max Unit — — — — — ns — 31/37 GS816218/36B(B/D) © 2004, GSI Technology ...

Page 32

... Package Dimensions—119-Bump FPBGA (Package B, Variation 2 A1 TOP VIEW SEATING PLANE C Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. BOTTOM VIEW A1 Ø0. Ø0. Ø0.60~0.90 (119x 7.62 14±0.10 A 0.20(4x) 32/37 GS816218/36B(B/ 1.27 © 2004, GSI Technology ...

Page 33

... Package Dimensions—165-Bump FPBGA (Package D) A1 TOP SEATING C Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. BOTTOM Ø0. Ø0. Ø0.40~0. 1.0 10. 13±0.0 B 0.20(4 33/37 GS816218/36B(B/ 1.0 © 2004, GSI Technology ...

Page 34

... GSI offers other versions this type of device in many different configurations and with a variety of different features, only some of which are covered in this data sheet. See the GSI Technology web site (www.gsitechnology.com) for a complete listing of current offerings Rev: 1.07 9/2008 Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com. ...

Page 35

... GS816218BD-250 GS816218BD-200 GS816218BD-150 512K x 36 GS816236BD-250 512K x 36 GS816236BD-200 512K x 36 GS816236BD-150 GS816218BD-250I GS816218BD-200I GS816218BD-150I 512K x 36 GS816236BD-250I 512K x 36 GS816236BD-200I 512K x 36 GS816236BD-150I GS816218BGD-250 GS816218BGD-200 GS816218BGD-150 512K x 36 GS816236BGD-250 Notes: 1. Customers requiring delivery in Tape and Reel should add the character “T” to the end of the part number. Example: GS816236BD-200IT. ...

Page 36

Page 37

... Changed Pin 16 from VDD to NC Content • Added (MCL) Must Connect Low to pin description • Rev. 1.06a Updated Mechanical Drawing Content • Rev. 1.06a Removed Status column from Ordering Information table • Updated for MP status Content 37/37 GS816218/36B(B/D) Page;Revisions;Reason © 2004, GSI Technology ...

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