W234X Cypress Semiconductor Corp, W234X Datasheet - Page 4

• Manufacturer Part Number: W234X
• Description: CLOCK GEN DIR RAMBS DUAL 28TSSOP
• Manufacturer: Cypress Semiconductor Corp
• Type: Direct RAMbus Clock Generatorr

Specifications of W234X

• Input: CMOS
• Output: CMOS
• Frequency - Max: 400MHz
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-TSSOP
• Frequency-max: 400MHz
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1398

Phase Detector Signals
The DRCG Phase Detector (
core logic, PCLKM (Pclk/M) and SYNCLKN (Synclk/N). The M
and N dividers in the core logic are chosen so that the frequen-
cies of PCLKM and SYNCLKN are identical. The Phase De-
tector (
clocks, and drives the DRCG Phase Aligner to null the input
phase error through the distributed loop. When the loop is
locked, the input phase error between PCLKM and SYNCLKN
is within the specification t
lock time given in the State Transition Section.
The Phase Detector (
the rising edge of SYNCLKN. The duty cycle of the phase de-
tector input clocks will be within the specification DC
en in Table 12. Because the duty cycles of the two phase de-
tector input clocks will not necessarily be identical, the falling
edges of PCLKM and SYNCLKN may not be aligned when the
rising edges are aligned.
The voltage levels of the PCLKM and SYNCLKN signals are
determined by the controller. The pin VDDIPD is used as the
voltage reference for the phase detector inputs and should be
connected to the output voltage supply of the controller. In
some applications, the DRCG PLL output clock will be used
directly, by bypassing the Phase Aligner. If PCLKM and SYN-
CLKN are not used, those inputs must be grounded.
Selection Logic
Table 1 shows the logic for selecting the PLL prescaler and
feedback dividers to determine the multiply ratio for the PLL
from the input Refclk. Divider A sets the feedback and divider
B sets the prescaler, so the PLL output clock frequency is set
by: PLLClk=Refclk*A/B.
Document #: 38-07232 Rev. *B
D
) detects the phase difference between the two input
D
) aligns the rising edge of PCLKM to
ERR,PD
D
) receives two inputs from the
CY2210-2
CY2210-3
CY2215
W133
W158
W159
W161
W167B
given in Table 13 after the
RMC
Pclk
Figure 3. DDLL Including Details of DRCG.
Refclk
IN,PD
W234
PLL
M
Gear
Ratio
Logic
giv-
N
Phase
Align
D
Synclk
Table 1. PLL Divider Selection
Table 2 shows the logic for enabling the clock outputs, using
the STOP# input signal. When STOP# is HIGH, the DRCG is
in its normal mode, and CLK and CLK# are complementary
outputs following the Phase Aligner output (PAclk). When
STOP# is LOW, the DRCG is in the Clk Stop mode, the output
clock drivers are disabled (set to Hi-Z), and the CLK and CLK#
settle to the DC voltage V
of V
Table 2. Clk Stop Mode Selection
Table 3 shows the logic for selecting the Bypass and Test
modes. The select bits, S0, S1, and S2 control the selection of
these modes. The Bypass mode brings out the full-speed PLL
output clock, bypassing the Phase Aligner. The Test mode
brings the REFCLK input all the way to the output, bypassing
both the PLL and the Phase Aligner. In the Output Test mode
(OE), both the CLK and CLK# outputs are put into a high-
impedance state (Hi-Z). This can be used for component test-
ing and for board-level testing.
MULT0
Clk Stop
Normal
X,STOP
Mode
0
0
0
0
1
1
1
1
S0/S1/S2 STOP#
4
is set by an external resistor network.
DLL
MULT1
RAC
0
0
1
1
0
0
1
1
STOP#
1
0
Busclk
X,STOP
MULT2
0
1
0
1
0
1
0
1
as given in Table 13. The level
V
PACLK
X,STOP
CLK
16
A
4
9
6
8
8
TBD
TBD
Page 4 of 14
PACLK#
V
CLK#
X,STOP
W234
B
1
2
1
3
3
1