ADF4360-8BCPZ Analog Devices Inc, ADF4360-8BCPZ Datasheet - Page 4

• Manufacturer Part Number: ADF4360-8BCPZ
• Description: IC SYNTHESIZER VCO 24-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Fanout Distribution, Integer N Synthesizer (RF)r

Specifications of ADF4360-8BCPZ

• Pll: Yes
• Input: CMOS
• Output: Clock
• Number Of Circuits: 1
• Ratio - Input:output: 1:2
• Differential - Input:output: No/No
• Frequency - Max: 400MHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 24-LFCSP
• Frequency-max: 400MHz
• Pll Type: Frequency Synthesis
• Frequency: 400MHz
• Supply Current: 5mA
• Supply Voltage Range: 3V To 3.6V
• Digital Ic Case Style: LFCSP
• No. Of Pins: 24
• Operating Temperature Range: -40°C To +85°C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: EVAL-ADF4360-8EBZ1 - BOARD EVALUATION FOR ADF4360-8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADF4360-8
Parameter
NOISE CHARACTERISTICS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
Operating temperature range is –40°C to +85°C.
Guaranteed by design. Sample tested to ensure compliance.
I
T
Unless otherwise stated, these characteristics are guaranteed for VCO core power = 5 mA. L1, L2 = 270 nH, 470 Ω resistors to GND in parallel with L1, L2.
Jumping from 88 MHz to 108 MHz. PFD frequency = 200 kHz; loop bandwidth = 10 kHz.
For more detail on using tuned loads, see the Output Matching section.
Using 50 Ω resistors to V
The noise of the VCO is measured in open-loop conditions.
CP
The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value). The
The phase noise is measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REF
f
f
The spurious signals are measured with the EVAL-ADF4360-xEB1 Evaluation Board and the HP 8562E Spectrum Analyzer. The Spectrum Analyzer provides the REF
for the synthesizer; f
phase noise figure of merit subtracts 10 log (PFD frequency).
synthesizer; offset frequency = 1 kHz.
A
REFIN
REFIN
Harmonic Content (Third)
Output Power
Output Power
Output Power Variation
VCO Tuning Range
VCO Phase Noise Performance
Synthesizer Phase Noise Floor
Phase Noise Figure of Merit
In-Band Phase Noise
RMS Integrated Phase Error
Spurious Signals due to PFD
Level of Unlocked Signal with
= 25°C; AV
is internally modified to maintain constant loop gain over the frequency range.
Frequency
MTLD Enabled
= 10 MHz; f
= 10 MHz; f
DD
= DV
PFD
PFD
12, 14
5, 7
5, 8
= 200 kHz; N = 1000; loop B/W = 10 kHz.
= 1 MHz; N = 120; loop B/W = 100 kHz.
DD
REFOUT
= V
VCO
11, 12
VCO
= 10 MHz @ 0 dBm.
, into a 50 Ω load.
5
= 3.3 V.
10
13
10
9
B Version
−21
−9/0
−14/−9
±3
1.25/2.5
−120
−139
−140
−142
−160
−150
−142
−215
−102
0.09
−75
−70
Unit
dBc typ
dBm typ
dBm typ
dB typ
V min/max
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
dBc/Hz typ
Degrees typ
dBc typ
dBm typ
Rev. A | Page 4 of 24
Conditions/Comments
Using tuned load, programmable in 3 dB steps; see Table 7
Using 50 Ω resistors to V
@ 100 kHz offset from carrier
@ 800 kHz offset from carrier
@ 3 MHz offset from carrier
@ 10 MHz offset from carrier
@ 200 kHz PFD frequency
@ 1 MHz PFD frequency
@ 8 MHz PFD frequency
@ 1 kHz offset from carrier
100 Hz to 100 kHz
VCO
, programmable in 3 dB steps; see Table 7
IN
for the
IN