AD9517-4BCPZ Analog Devices Inc, AD9517-4BCPZ Datasheet - Page 29

• Manufacturer Part Number: AD9517-4BCPZ
• Description: IC CLOCK GEN 1.8GHZ VCO 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-4BCPZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.8GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 1.8GHz
• No. Of Outputs: 12
• Supply Current: 100µA
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Rohs Compliant: Yes
• For Use With: AD9517-4/PCBZ - BOARD EVALUATION AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REFIN (REF1)
REFIN (REF2)
Internal VCO and Clock Distribution
When using the internal VCO and PLL, the VCO divider must
be employed to ensure that the frequency presented to the channel
dividers does not exceed its specified maximum frequency
(1600 MHz, see Table 3). The internal PLL uses an external loop
filter to set the loop bandwidth. The external loop filter is also
crucial to the loop stability.
When using the internal VCO, it is necessary to calibrate the
VCO (Register 0x018[0]) to ensure optimal performance.
For internal VCO and clock distribution applications, the
register settings shown in Table 24 should be used.
BYPASS
RESET
SYNC
SCLK
SDIO
SDO
CLK
CLK
PD
CS
LF
REF1
REF2
REGULATOR (LDO)
LOW DROPOUT
VCO
AD9517-4
CONTROL
DIGITAL
SERIAL
SWITCHOVER
STATUS
LOGIC
REFERENCE
PORT
REF_ SEL
STATUS
VS
PRESCALER
2, 3, 4, 5, OR 6
1
P, P + 1
DIVIDE BY
GND
0
VCO STATUS
N DIVIDER
DIVIDER
R
Figure 43. Internal VCO and Clock Distribution
COUNTERS
DISTRIBUTION
DIVIDE BY
DIVIDE BY
REFERENCE
1 TO 32
1 TO 32
A/B
RSET
Rev. B | Page 29 of 80
DIVIDE BY
DIVIDE BY
1 TO 32
1 TO 32
PROGRAMMABLE
PROGRAMMABLE
R DELAY
N DELAY
REFMON
Table 24. Settings When Using Internal VCO
Register
0x010[1:0] = 00b
0x010 to 0x1E
0x018[0] = 0,
0x232[0] = 1
0x1E0[2:0]
0x1E1[0] = 0b
0x1E1[1] = 1b
0x018[0] = 1,
0x232[0] = 1
DIVIDE BY
DIVIDE BY
1 TO 32
1 TO 32
FREQUENCY
DETECTOR
DETECT
PHASE
LOCK
Function
PLL normal operation (PLL on).
PLL settings. Select and enable a reference
input; set R, N (P, A, B), PFD polarity, and I
according to the intended loop configuration.
Reset VCO calibration (this does not have to
be done first time after power-up, but must
be done subsequently).
VCO divider set to divide-by-2, divide-by-3,
divide-by-4, divide-by-5, and divide-by-6.
Use the VCO divider as source for
distribution section.
VCO selected as the source.
Initiate VCO calibration.
CPRSET VCP
ΔT
ΔT
ΔT
ΔT
CHARGE
PUMP
LVDS/CMOS
LVDS/CMOS
HOLD
LVPECL
LVPECL
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4 (OUT4A)
OUT4 (OUT4B)
OUT5 (OUT5A)
OUT5 (OUT5B)
OUT6 (OUT6A)
OUT6 (OUT6B)
OUT7 (OUT7A)
OUT7 (OUT7B)
LD
CP
STATUS
AD9517-4
CP