AD9517-4/PCBZ

Manufacturer Part NumberAD9517-4/PCBZ
DescriptionBOARD EVALUATION AD9517-4
ManufacturerAnalog Devices Inc
AD9517-4/PCBZ datasheet
 


Specifications of AD9517-4/PCBZ

Design ResourcesHigh Performance, Dual Channel IF Sampling Receiver (CN0140)Main PurposeTiming, Clock Generator
Utilized Ic / PartAD9517-4Lead Free Status / RoHS StatusLead free / RoHS Compliant
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FEATURES
Low phase noise, phase-locked loop (PLL)
On-chip VCO tunes from 1.45 GHz to 1.80 GHz
External VCO/VCXO to 2.4 GHz optional
1 differential or 2 single-ended reference inputs
Reference monitoring capability
Auto and manual reference switchover/holdover modes
Autorecover from holdover
Accepts LVPECL, LVDS, or CMOS references to 250 MHz
Programmable delays in path to PFD
Digital or analog lock detect, selectable
2 pairs of 1.6 GHz LVPECL outputs
Each output pair shares a 1-to-32 divider with coarse
phase delay
Additive output jitter 225 fs rms
Channel-to-channel skew paired outputs of <10 ps
2 pairs of 800 MHz LVDS clock outputs
Each output pair shares two cascaded 1-to-32 dividers
with coarse phase delay
Additive output jitter 275 fs rms
Fine delay adjust (Δt) on each LVDS output
Eight 250 MHz CMOS outputs (two per LVDS output)
Automatic synchronization of all outputs on power-up
Manual synchronization of outputs, as needed
Serial control port
Available in a 48-lead LFCSP
APPLICATIONS
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
10/40/100 Gb/sec networking line cards, including SONET,
Synchronous Ethernet, OTU2/3/4
High performance instrumentation
Broadband infrastructure
ATE
GENERAL DESCRIPTION
1
The AD9517-4
provides a multi-output clock distribution
function with subpicosecond jitter performance, along with an
on-chip PLL and VCO. The on-chip VCO tunes from 1.45 GHz
to 1.80 GHz. Optionally, an external VCO/VCXO of up to
2.4 GHz can be used.
The AD9517-4 emphasizes low jitter and phase noise to
maximize data converter performance, and it can benefit other
applications with demanding phase noise and jitter requirements.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
12-Output Clock Generator with
Integrated 1.6 GHz VCO
FUNCTIONAL BLOCK DIAGRAM
CP
REF1
REFIN
VCO
REF2
DIVIDER
CLK
AND MUXs
DIV/Φ
LVPECL
DIV/Φ
LVPECL
Δt
DIV/Φ
DIV/Φ
LVDS/CMOS
Δt
Δt
DIV/Φ
DIV/Φ
LVDS/CMOS
Δt
SERIAL CONTROL PORT
AND
AD9517-4
DIGITAL LOGIC
Figure 1.
The AD9517-4 features four LVPECL outputs (in two pairs)
and four LVDS outputs (in two pairs). Each LVDS output can
be reconfigured as two CMOS outputs. The LVPECL outputs
operate to 1.6 GHz, the LVDS outputs operate to 800 MHz, and
the CMOS outputs operate to 250 MHz.
Each pair of outputs has dividers that allow both the divide
ratio and coarse delay (or phase) to be set. The range of division
for the LVPECL outputs is 1 to 32. The LVDS/CMOS outputs
allow a range of divisions up to a maximum of 1024.
The AD9517-4 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. An external VCO, which
requires an extended voltage range, can be accommodated
by connecting the charge pump supply (VCP) to 5 V. A separate
LVPECL power supply can be from 2.5 V to 3.3 V (nominal).
The AD9517-4 is specified for operation over the industrial
range of −40°C to +85°C.
1
AD9517 is used throughout to refer to all the members of the AD9517
family. However, when AD9517-4 is used, it is referring to that specific
member of the AD9517 family.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
©2007–2010 Analog Devices, Inc. All rights reserved.
AD9517-4
LF
STATUS
MONITOR
OUT0
OUT1
OUT2
OUT3
OUT4
OUT5
OUT6
OUT7
www.analog.com

AD9517-4/PCBZ Summary of contents

  • Page 1

    ... The AD9517-4 is specified for operation over the industrial range of −40°C to +85°C. 1 AD9517 is used throughout to refer to all the members of the AD9517 family. However, when AD9517-4 is used referring to that specific member of the AD9517 family. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. ...

  • Page 2

    ... Control Register Map Overview .............................................. 55 Control Register Map Descriptions ......................................... 58   Applications Information .............................................................. 75   Frequency Planning Using the AD9517 .................................. 75   Using the AD9517 Outputs for ADC Clock Applications .... 75   LVPECL Clock Distribution ..................................................... 76   LVDS Clock Distribution .......................................................... 76   CMOS Clock Distribution ........................................................ 77   Outline Dimensions ....................................................................... 78   ...

  • Page 3

    ... Changes to Table 57 ........................................................................ 69 Changes to Table 58 ........................................................................ 71 Changes to Table 59 ........................................................................ 72 Changes to Table 60 and Table 61 ................................................. 74 Added Frequency Planning Using the AD9517 Section ............ 75 Changes to Figure 70 and Figure 72; Added Figure 71 .............. 76 Changes to LVDS Clock Distribution Section ............................ 76 Added Exposed Paddle Notation to Outline Dimensions ......... 78 Changes to Ordering Guide ........................................................... 78 7/07— ...

  • Page 4

    ... AD9517-4 SPECIFICATIONS Typical (typ) is given for 3.3 V ± 5 S_LVPECL Minimum (min) and maximum (max) values are given over full V POWER SUPPLY REQUIREMENTS Table 1. Parameter S_LVPECL V CP RSET Pin Resistor CPRSET Pin Resistor BYPASS Pin Capacitor PLL CHARACTERISTICS Table 2. Parameter VCO (ON-CHIP) ...

  • Page 5

    ... Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[ 3.5 ns Register 0x017[1:0] = 10b; Register 0x018[ Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[ Register 0x017[1:0] = 00b, 01b, 11b; Register 0x018[ Register 0x017[1:0] = 10b; Register 0x018[ Rev Page 5.1 kΩ RSET = < V − 0 < V − 0 Table 54 AD9517 PFD ...

  • Page 6

    ... Test Conditions/Comments Termination = 50 Ω − Differential (OUT, OUT) Using direct to output; see Figure 25 Differential termination 100 Ω @ 3.5 mA Differential (OUT, OUT) The AD9517 outputs toggle at higher frequencies, but the output amplitude may not meet the V specification V − V measurement across a differential pair the default amplitude setting with output driver not toggling ...

  • Page 7

    ... Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 000000b 1.72 2.31 2.89 ns Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 001100b 5.7 8.0 10.1 ns Register 0x0A2 (0x0A5) (0x0A8) (0x0AB) [5:0] 101111b 0.23 ps/°C −0.02 ps/°C 0.3 ps/°C 0.24 ps/°C Rev Page AD9517-4 − level = 810 LOAD = 10 pF LOAD ...

  • Page 8

    ... AD9517-4 CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED) Table 6. Parameter CLK-TO-LVPECL ADDITIVE PHASE NOISE CLK = 1 GHz, OUTPUT = 1 GHz Divider = Offset @ 100 Hz Offset @ 1 kHz Offset @ 10 kHz Offset @ 100 kHz Offset @ 1 MHz Offset @ 10 MHz Offset @ 100 MHz Offset CLK = 1 GHz, OUTPUT = 200 MHz ...

  • Page 9

    ... Rev Page AD9517-4 Test Conditions/Comments Input slew rate > 1 V/ns Test Conditions/Comments Internal VCO; direct to LVPECL output ...

  • Page 10

    ... AD9517-4 CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK GENERATION USING INTERNAL VCO) Table 8. Parameter LVPECL OUTPUT ABSOLUTE TIME JITTER VCO = 1475 MHz; LVPECL = 491.52 MHz; PLL LBW = 135 kHz VCO = 1475 MHz; LVPECL = 122.88 MHz; PLL LBW = 135 kHz VCO = 1475 MHz; LVPECL = 61.44 MHz; PLL LBW = 135 kHz CLOCK OUTPUT ABSOLUTE TIME JITTER (CLOCK CLEANUP USING INTERNAL VCO) Table 9 ...

  • Page 11

    ... Distribution section only; does not include PLL and VCO; uses rising edge of clock signal 285 fs rms Calculated from SNR of ADC method Distribution section only; does not include PLL and VCO; uses rising edge of clock signal 350 fs rms Calculated from SNR of ADC method Rev Page AD9517-4 ...

  • Page 12

    ... AD9517-4 DELAY BLOCK ADDITIVE TIME JITTER Table 13. Parameter 1 DELAY BLOCK ADDITIVE TIME JITTER 100 MHz Output Delay (1600 μA, 1C) Fine Adj. 000000 Delay (1600 μA, 1C) Fine Adj. 101111 Delay (800 μA, 1C) Fine Adj. 000000 Delay (800 μA, 1C) Fine Adj. 101111 Delay (800 μA, 4C) Fine Adj. 000000 Delay (800 μ ...

  • Page 13

    ... MHz 8 kHz 1.6 V 260 mV Rev Page AD9517-4 Test Conditions/Comments These pins each have a 30 kΩ internal pull-up resistor High speed clock is CLK input signal Test Conditions/Comments When selected as a digital output (CMOS); there are other modes in which these pins are not CMOS digital outputs; see Table 54, ...

  • Page 14

    ... AD9517-4 POWER DISSIPATION Table 17. Parameter POWER DISSIPATION, CHIP Power-On Default Full Operation; CMOS Outputs at 229 MHz Full Operation; LVDS Outputs at 200 MHz PD Power-Down PD Power-Down, Maximum Sleep V Supply CP POWER DELTAS, INDIVIDUAL FUNCTIONS VCO Divider REFIN (Differential) REF1, REF2 (Single-Ended) VCO PLL Channel Divider ...

  • Page 15

    ... TIMING DIAGRAMS t CLK CLK t PECL t LVDS t CMOS Figure 2. CLK/ CLK to Clock Output Timing, DIV = 1 DIFFERENTIAL 80% LVPECL 20 Figure 3. LVPECL Timing, Differential t FP Rev Page DIFFERENTIAL 80% LVDS 20 Figure 4. LVDS Timing, Differential SINGLE-ENDED 80% CMOS 10pF LOAD 20 Figure 5. CMOS Timing, Single-Ended Load AD9517-4 ...

  • Page 16

    ... AD9517-4 ABSOLUTE MAXIMUM RATINGS Table 18. Parameter VS, VS_LVPECL to GND VCP to GND REFIN, REFIN to GND REFIN to REFIN RSET to GND CPRSET to GND CLK, CLK to GND CLK to CLK SCLK, SDIO, SDO GND OUT0, OUT0, OUT1, OUT1, OUT2, OUT2, OUT3, OUT3,OUT4, OUT4, OUT5, OUT5, OUT6, OUT6, OUT7, OUT7 to GND ...

  • Page 17

    ... Along with CLK, this is the self-biased differential input for the clock distribution section. Serial Control Port Data Clock Signal. Serial Control Port Chip Select; Active Low. This pin has an internal 30 kΩ pull-up resistor. Rev Page AD9517-4 36 OUT4 (OUT4A) 35 OUT4 (OUT4B) 34 ...

  • Page 18

    ... AD9517-4 Input/ Pin No. Output Pin Type Mnemonic 15 O 3.3 V CMOS SDO 16 I/O 3.3 V CMOS SDIO 17 I 3.3 V CMOS RESET 18 I 3.3 V CMOS PD 21 Power VS_LVPECL 42 O LVPECL OUT0 41 O LVPECL OUT0 39 O LVPECL OUT1 38 O LVPECL OUT1 19 O LVPECL OUT2 20 O LVPECL ...

  • Page 19

    ... VOLTAGE ON CP PIN (V) Figure 11. Charge Pump Characteristics @ V 5.0 4.5 4.0 3.5 PUMP DOWN PUMP UP 3.0 2.5 2.0 1.5 1.0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VOLTAGE ON CP PIN (V) Figure 12. Charge Pump Characteristics @ V AD9517-4 1.75 3 4.0 4.5 5 ...

  • Page 20

    ... AD9517-4 –140 –145 –150 –155 –160 –165 –170 0.1 1 PFD FREQUENCY (MHz) Figure 13. PFD Phase Noise Referred to PFD Input vs. PFD Frequency –210 –212 –214 –216 –218 –220 –222 –224 0 0.5 1.0 1.5 SLEW RATE (V/ns) Figure 14. PLL Figure of Merit (FOM) vs. Slew Rate at REFIN/ REFIN 2 ...

  • Page 21

    ... TIME (ns) Figure 21. LVDS Output (Differential) @ 100 MHz 0.4 0.2 0 –0.2 –0 Figure 22. LVDS Output (Differential) @ 800 MHz 2.8 1.8 0.8 –0 2.8 1.8 0.8 –0 Rev Page AD9517 TIME (ns 100 TIME (ns) Figure 23. CMOS Output @ 25 MHz TIME (ns) Figure 24. CMOS Output @ 250 MHz 1 2 ...

  • Page 22

    ... AD9517-4 1600 1400 1200 1000 800 0 1 FREQUENCY (GHz) Figure 25. LVPECL Differential Swing vs. Frequency 700 600 500 0 100 200 300 400 500 FREQUENCY (MHz) Figure 26. LVDS Differential Swing vs. Frequency 100 200 300 OUTPUT FREQUENCY (MHz) Figure 27. CMOS Output Swing vs. Frequency and Capacitive Load – ...

  • Page 23

    ... Figure 35. Phase Noise (Additive) LVDS @ 800 MHz, Divide-by-2 –120 –130 –140 –150 –160 –170 10 10M 100M Figure 36. Phase Noise (Additive) CMOS @ 50 MHz, Divide-by-20 Rev Page AD9517-4 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100 1k 10k 100k 1M 10M FREQUENCY (Hz) 100 1k ...

  • Page 24

    ... AD9517-4 –100 –110 –120 –130 –140 –150 –160 10 100 1k 10k 100k FREQUENCY (Hz) Figure 37. Phase Noise (Additive) CMOS @ 250 MHz, Divide-by-4 –120 –130 –140 –150 –160 1k 10k 100k 1M FREQUENCY (Hz) Figure 38. Phase Noise (Absolute) Clock Generation; Internal VCO @ 1.475 GHz; PFD = 15.36 MHz; LBW = 135 kHz; LVPECL Output = 122.88 MHz – ...

  • Page 25

    ... In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. Rev Page AD9517-4 ...

  • Page 26

    ... REFIN (REF1) REFIN (REF2) LOW DROPOUT BYPASS REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9517-4 GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE COUNTERS N DELAY N DIVIDER DIVIDE DIVIDE BY ...

  • Page 27

    ... THEORY OF OPERATION OPERATIONAL CONFIGURATIONS The AD9517 can be configured in several ways. These configurations must be set up by loading the control registers (see Table 52 and Table 53 through Table 62). Each section or function must be individually programmed by setting the appropriate bits in the corresponding control register or registers. High Frequency Clock Distribution—CLK or External VCO > ...

  • Page 28

    ... REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9517-4 Figure 42. High Frequency Clock Distribution or External VCO > 1600 MHz GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS PROGRAMMABLE A/B N DELAY COUNTERS N DIVIDER ...

  • Page 29

    ... Figure 43. Internal VCO and Clock Distribution Table 24. Settings When Using Internal VCO Register 0x010[1:0] = 00b 0x010 to 0x1E 0x018[ 0x232[ 0x1E0[2:0] 0x1E1[ 0x1E1[ 0x018[ 0x232[ Rev Page AD9517-4 CPRSET VCP LD LOCK DETECT HOLD PHASE CHARGE FREQUENCY CP PUMP DETECTOR STATUS OUT0 OUT0 LVPECL ...

  • Page 30

    ... REFIN (REF1) REFIN (REF2) LOW DROPOUT BYPASS REGULATOR (LDO) PRESCALER LF VCO CLK CLK PD DIGITAL SYNC LOGIC RESET SCLK SERIAL SDIO CONTROL SDO PORT CS AD9517-4 GND RSET REFMON DISTRIBUTION REFERENCE R PROGRAMMABLE DIVIDER R DELAY VCO STATUS A/B PROGRAMMABLE COUNTERS N DELAY N DIVIDER DIVIDE DIVIDE BY ...

  • Page 31

    ... Function PFD polarity positive (higher control voltage 0x010[ produces higher frequency) PFD polarity negative (higher control 0x010[ voltage produces lower frequency) After the appropriate register values are programmed, Register 0x232 must be set to 0x01 for the values to take effect. Rev Page AD9517-4 ...

  • Page 32

    ... ADIsimCLK™ (V1.2 or later free program that can help with the design and exploration of the capabilities and features of the AD9517, including the design of the PLL loop filter available at www.analog.com/clocks. Phase Frequency Detector (PFD) The PFD takes inputs from the R counter and N counter and produces an output proportional to the phase and frequency difference between them ...

  • Page 33

    ... PUMP Figure 47. Example of External Loop Filter for a PLL Using an External VCO PLL Reference Inputs The AD9517 features a flexible PLL reference input circuit that allows either a fully differential input or two separate single-ended inputs. The input frequency range for the reference inputs is specified in Table 2. Both the differential and the single-ended inputs are self-biased, allowing for easy ac coupling of input signals ...

  • Page 34

    ... A and B. The total divider value × where P can 16, or 32. Prescaler The prescaler of the AD9517 allows for two modes of operation: a fixed divide (FD) mode and a dual modulus (DM) mode where the prescaler divides by P and ( and 3, 4 and 5, 8 and 9, 16 and 17 and 33}. The prescaler modes of operation are given in Table 54, Register 0x16[2:0] ...

  • Page 35

    ... VCO frequency is greater than 2400 MHz because the frequency going to the A/B counter is too high. When the AD9517 B counter is bypassed (B = 1), the A counter should be set to 0, and the overall resulting divide is equal to the prescaler setting, P. The possible divide ratios in this mode are 16, and 32 ...

  • Page 36

    ... The number of consecutive PFD cycles required for lock is programmable (Register 0x018[6:5]). Analog Lock Detect (ALD) The AD9517 provides an ALD function that can be selected for use at the LD pin. There are two versions of ALD, as follows: • N-channel open-drain lock detect. This signal requires a pull-up resistor to the positive supply, VS ...

  • Page 37

    ... Holdover The AD9517 PLL has a holdover function. Holdover is implemented by putting the charge pump into a high impedance state. This is useful when the PLL reference clock is lost. Holdover mode allows the VCO to maintain a relatively constant frequency even though there is no reference clock. Without this function, the charge pump is placed into a constant pump-up or pump-down state, resulting in a massive VCO frequency shift ...

  • Page 38

    ... Register 0x01D[0] = 1b; enable the holdover function. Frequency Status Monitors The AD9517 contains three frequency status monitors that are used to indicate if the PLL reference (or references in the case of single-ended mode) and the VCO have fallen below a threshold frequency. A diagram showing their location in the PLL is shown in Figure 53 ...

  • Page 39

    ... VCO CLK CLK VCO Calibration The AD9517 on-chip VCO must be calibrated to ensure proper operation over process and temperature. The VCO calibration is controlled by a calibration controller running off of a divided REFIN clock. The calibration requires that the PLL be set up properly to lock the PLL loop and that the REFIN clock be present. ...

  • Page 40

    ... Internal VCO or External CLK as Clock Source The clock distribution of the AD9517 has two clock input sources: an internal VCO or an external clock connected to the CLK/ CLK pins. Either the internal VCO or CLK must be chosen as the source of the clock signal to distribute ...

  • Page 41

    ... CLK 32) × ( × When a divider is bypassed 32) × Otherwise, D (2to 32) each channel divider to divide by any integer from 32) × ( × 32) Rev Page AD9517-4 for Divider 0 and Divider 1 X Low Cycles High Cycles M N Bypass 0x190[7:4] 0x190[3:0] 0x191[7] 0x196[7:4] 0x196[3:0] ...

  • Page 42

    ... AD9517-4 Duty Cycle and Duty-Cycle Correction (0, 1) The duty cycle of the clock signal at the output of a channel is a result of some or all of the following conditions: • What are the M and N values for the channel? • Is the DCC enabled? • Is the VCO divider used? • ...

  • Page 43

    ... If only one divider is needed when using Divider 2 and Divider 3, use the first one (X.1) and bypass the second one (X.2). Do not bypass X.1 and use X.2. Rev Page AD9517-4 × 1024. Divide-by-1 is achieved by X.1 X.2 ...

  • Page 44

    ... AD9517-4 Duty Cycle and Duty-Cycle Correction (Divider 2 and Divider 3) The same duty cycle and DCC considerations apply to Divider 2 and Divider Divider 0 and Divider 1 (see the Duty Cycle and Duty-Cycle Correction (0, 1) section); however, with these channel dividers, the number of possible configurations is even more complex ...

  • Page 45

    ... M X.1 Fine Delay Adjust (Divider 2 and Divider 3) ( X.1 X.2 X X%)/ Each AD9517 LVDS/CMOS output (OUT4 to OUT7) includes X.2 ((2N + 3)(2N + 3)) X.1 X.2 an analog delay element that can be programmed to give variable time delays (Δ VCO CLK DIVIDER DIVIDER High Cycles N ...

  • Page 46

    ... VCO divider) and an uncertainty one cycle of the clock at the input to the channel divider due to the asynchronous nature of the SYNC signal with respect to the clock edges inside the AD9517. The delay from the output clocking is between 14 and 15 cycles of clock at the channel divider input, plus either one cycle of the VCO divider ...

  • Page 47

    ... SYNC operation. Between outputs and after synchronization, this allows for the setting of phase offsets. The AD9517 outputs are in pairs, sharing a channel divider per pair (two pairs of pairs, four outputs, in the case of CMOS). The synchronization conditions apply to both outputs of a pair. ...

  • Page 48

    ... CMOS B output can be powered on or off separately. OUT OUT RESET MODES The AD9517 has several ways to force the chip into a reset condition that restores all registers to their default values and makes these settings active. Power-On Reset—Start-Up Conditions When V A power-on reset (POR) is issued when the V turned on ...

  • Page 49

    ... LVPECL output circuitry from damage that could be caused by certain termination and load configurations when tristated. Because this is not a complete power-down, it can be called sleep mode. When the AD9517 power-down, the chip is in the following state: • The PLL is off (asynchronous power-down). • ...

  • Page 50

    ... PORT SDIO 16 Figure 61. Serial Control Port GENERAL OPERATION OF SERIAL CONTROL PORT A write or a read operation to the AD9517 is initiated by pulling CS low. CS stalled high is supported in modes where three or fewer bytes of data (plus instruction data) are transferred (see CS can temporarily return high on any byte ...

  • Page 51

    ... In MSB first mode, subsequent bytes increment the address. MSB/LSB FIRST TRANSFERS The AD9517 instruction word and byte data can be MSB first or LSB first. Any data written to Register 0x000 must be mirrored; the upper four bits (Bits[7:4]) must mirror the lower four bits (Bits[3:0) ...

  • Page 52

    ... AD9517-4 Table 49. Serial Control Port, 16-Bit Instruction Word, MSB First MSB I15 I14 I13 I12 R A12 = 0 CS SCLK DON'T CARE SDIO R A12 A11 A10 DON'T CARE 16-BIT INSTRUCTION HEADER Figure 63. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data ...

  • Page 53

    ... Minimum period that SCLK should logic high state HIGH t Minimum period that SCLK should logic low state LOW t SCLK to valid SDIO and SDO (see Figure 66 CLK t t HIGH LOW t DH BIT N BIT Figure 68. Serial Control Port Timing—Write Rev Page AD9517 ...

  • Page 54

    ... Junction-to-top-of-package characterization parameter, 1.0 m/sec airflow per JEDEC JESD51-2 (still air) JT Ψ Junction-to-top-of-package characterization parameter, 2.0 m/sec airflow per JEDEC JESD51-2 (still air) JT The AD9517 is specified for a case temperature (T that T is not exceeded, an airflow source can be used. CASE Use the following equation to determine the junction ...

  • Page 55

    ... REF1 Differential power-on power-on reference Holdover External Holdover enable holdover enable control REF2 REF1 Digital frequency > frequency > lock detect threshold threshold AD9517-4 Default Value (Hex) 0x18 0xD3 0x00 0x7D 0x01 0x00 0x00 0x03 0x00 0x06 0x00 0x06 0x00 0x00 0x00 0x00 ...

  • Page 56

    ... AD9517-4 Reg. Addr. (Hex) Parameter Bit 7 (MSB) Bit 6 Fine Delay Adjust—OUT4 to OUT7 0x0A0 OUT4 delay bypass 0x0A1 OUT4 delay Blank full-scale 0x0A2 OUT4 delay Blank fraction 0x0A3 OUT5 delay bypass 0x0A4 OUT5 delay Blank full-scale 0x0A5 OUT5 delay Blank fraction ...

  • Page 57

    ... Blank Reserved Power- Power-down down VCO clock clock input interface section Blank Reserved Blank Blank Rev Page AD9517-4 Bit 2 Bit 1 Bit 0 (LSB) Divider 0 high cycles Divider 0 phase offset Divider 0 Divider 0 direct to DCCOFF output Divider 1 high cycles Divider 1 phase offset Divider 1 Divider 1 ...

  • Page 58

    ... Selects unidirectional or bidirectional data transfer mode. 0: SDIO pin used for write and read; SDO set high impedance; bidirectional mode (default). 1: SDO used for read, SDIO used for write; unidirectional mode. Uniquely identifies the dash version (-0 through -4) of the AD9517 AD9517-0: 0x11 AD9517-1: 0x51 ...

  • Page 59

    ... Charge Pump Mode 0 High impedance state. 1 Force source current (pump up). 0 Force sink current (pump down). 1 Normal operation (default). 0 Mode 0 Normal operation. 1 Asynchronous power-down (default). 0 Normal operation. 1 Synchronous power-down. supply voltage. CP /2. CP Rev Page AD9517-4 ...

  • Page 60

    ... AD9517-4 Reg. Addr. (Hex) Bits Name Description 0x016 [2:0] Prescaler P Prescaler dual modulus and FD = fixed divide 0x017 [7:2] STATUS pin Select the signal that is connected to the STATUS pin. control Mode Prescaler Divide-by- Divide-by- Divide-by-2 (2/3 mode Divide-by-4 (4/5 mode Divide-by-8 (8/9 mode). ...

  • Page 61

    ... PFD Cycles to Determine Lock 0 5 (default). 1 16. 0 64. 1 255. 1 VCO Calibration Clock Divider (default). 6 Action 0 Do nothing on SYNC (default). 1 Asynchronous reset. 0 Synchronous reset nothing on SYNC . Table 2 ) (default = 0x00). Table 2 ) (default = 0x00). Table 16 Rev Page REF1, REF2, and VCO frequency status monitor). AD9517-4 ...

  • Page 62

    ... AD9517-4 Reg. Addr. (Hex) Bits Name Description 0x01A [5:0] LD pin control Select the signal that is connected to the LD pin 0x01B 7 VCO Enable or disable VCO frequency monitor. frequency monitor 0: disable VCO frequency monitor (default). 1: enable VCO frequency monitor. 6 REF2 ( REFIN ) Enable or disable REF2 frequency monitor. ...

  • Page 63

    ... AND (Status of selected reference) AND (Status of VCO LVL Status of VCO frequency (active low LVL Selected reference (low = REF2, high = REF1 LVL Digital lock detect (DLD); active low LVL Holdover active (active low LVL LD pin comparator output (active low). Rev Page AD9517-4 ...

  • Page 64

    ... AD9517-4 Reg. Addr. (Hex) Bits Name Description 0x01C 1 REF1 power-on When automatic reference switchover is disabled, this bit turns the REF1 power on. 0: REF1 power off (default). 1: REF1 power on. 0 Differential Selects the PLL reference mode, differential or single-ended. Single-ended must be selected for the automatic reference switchover or REF1 and REF2 to work ...

  • Page 65

    ... Bypass or use the delay function. 0: use delay function. 1: bypass delay function (default). Selects the number of ramp capacitors used by the delay function. The combination of the number of the capacitors and the ramp current sets the delay full scale Number of Capacitors (default Rev Page AD9517-4 ...

  • Page 66

    ... AD9517-4 Reg. Addr. (Hex) Bits Name 0x0A4 [2:0] OUT5 ramp current 0x0A5 [5:0] OUT5 delay fraction 0x0A6 0 OUT6 delay bypass 0x0A7 [5:3] OUT6 ramp capacitors [2:0] OUT6 ramp current 0x0A8 [5:0] OUT6 delay fraction 0x0A9 0 OUT7 delay bypass Description Ramp current for the delay function. The combination of the number of capacitors and the ramp current sets the delay full scale ...

  • Page 67

    ... LVPECL power-down modes Mode 0 0 Normal operation (default Partial power-down, reference on; use only if there are no external load resistors Partial power-down, reference on, safe LVPECL power-down Total power-down, reference off; use only if there are no external load resistors. Rev Page AD9517 Output On Off Off Off ...

  • Page 68

    ... AD9517-4 Reg. Addr. (Hex) Bits Name 0x0F1 4 OUT1 invert [3:2] OUT1 LVPECL differential voltage [1:0] OUT1 power-down 0x0F4 4 OUT2 invert [3:2] OUT2 LVPECL differential voltage [1:0] OUT2 power-down 0x0F5 4 OUT3 invert [3:2] OUT3 LVPECL differential voltage [1:0] OUT3 power-down Description Sets the output polarity. ...

  • Page 69

    ... LVDS (default). 1: CMOS. Set output current level in LVDS mode. This has no effect in CMOS mode Current ( Rev Page AD9517-4 OUT4B (CMOS) OUT4 (LVDS) Inverting Noninverting Noninverting Noninverting (default) Inverting Noninverting Noninverting Noninverting Noninverting Inverting Inverting Inverting Noninverting Inverting Inverting Inverting Recommended Termination (Ω ...

  • Page 70

    ... AD9517-4 Reg. Addr. (Hex) Bits Name 0x141 0 OUT5 power-down 0x142 [7:5] OUT6 output polarity 4 OUT6 CMOS B 3 OUT6 select LVDS/CMOS [2:1] OUT6 LVDS output current 0 OUT6 power-down 0x143 [7:5] OUT7 output polarity 4 OUT7 CMOS B 3 OUT7 select LVDS/CMOS Description Power-down output (LVDS/CMOS). ...

  • Page 71

    ... Bypass and power-down the divider; route input to divider output. 0: use divider (default). 1: bypass divider. Nosync. 0: obey chip-level SYNC signal (default). 1: ignore chip-level SYNC signal. Force divider output to high. This requires that nosync (Bit 6) also be set. 0: divider output forced to low (default). 1: divider output forced to high. Rev Page AD9517-4 ...

  • Page 72

    ... AD9517-4 Reg. Addr. (Hex) Bits Name 0x197 4 Divider 1 start high [3:0] Divider 1 phase offset 0x198 1 Divider 1 direct to output 0 Divider 1 DCCOFF Table 59. LVDS/CMOS Channel Dividers Reg. Addr. (Hex) Bits Name 0x199 [7:4] Low Cycles Divider 2.1 [3:0] High Cycles Divider 2.1 0x19A [7:4] Phase Offset Divider 2 ...

  • Page 73

    ... Force Divider 3 output high. Requires that nosync also be set. 0: force low (default). 1: force high. Divider 3.2 start high/low. 0: start low (default). 1: start high. Divider 3.1 start high/low. 0: start low (default). 1: start high. Duty-cycle correction function. 0: enable duty-cycle correction (default). 1: disable duty-cycle correction. Rev Page AD9517-4 ...

  • Page 74

    ... AD9517-4 Table 60. VCO Divider and CLK Input Reg. Addr (Hex) Bits Name 0x1E0 [2:0] VCO divider 0x1E1 4 Power down clock input section 3 Power down VCO clock interface 2 Power down VCO and CLK 0x1E1 1 Select VCO or CLK 0 Bypass VCO divider Table 61. System Reg ...

  • Page 75

    ... MHz offset) for the same output frequency is usually less than 150 fs over the entire VCO frequency range (1.45 GHz to 2.95 GHz) of the AD9517 family. If the desired frequency plan can be achieved with a version of the AD9517 that has a lower VCO frequency, choosing the lower frequency part results in the lowest phase noise and the lowest jitter ...

  • Page 76

    ... LVDS CLOCK DISTRIBUTION V = 3.3V S The AD9517 provides four clock outputs (OUT4 to OUT7) that are selectable as either CMOS or LVDS level outputs. LVDS is a 50Ω differential output option that uses a current mode output stage. LVPECL 50Ω ...

  • Page 77

    ... MICROSTRIP Figure 74. Series Termination of CMOS Output Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9517 do not supply enough current to provide a full voltage swing with a low impedance resistive, far-end termination, as shown in Figure 75. The far-end termination network should match the PCB trace impedance and provide the desired switching point ...

  • Page 78

    ... TOP VIEW 12° MAX 1.00 0.85 0.80 SEATING PLANE ORDERING GUIDE 1 Model Temperature Range AD9517-4ABCPZ −40°C to +85°C AD9517-4ABCPZ-RL7 −40°C to +85°C AD9517-4A/PCBZ RoHS Compliant Part. 7.10 0.60 MAX 7.00 SQ 6.90 0.60 MAX 0.50 6.85 REF 6.75 SQ 6.65 0.50 0.40 ...

  • Page 79

    ... NOTES Rev Page AD9517-4 ...

  • Page 80

    ... AD9517-4 NOTES ©2007–2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06428-0-5/10(B) Rev Page ...