AD9517-4/PCBZ Analog Devices Inc, AD9517-4/PCBZ Datasheet - Page 38

• Manufacturer Part Number: AD9517-4/PCBZ
• Description: BOARD EVALUATION AD9517-4
• Manufacturer: Analog Devices Inc

Specifications of AD9517-4/PCBZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Main Purpose: Timing, Clock Generator
• Utilized Ic / Part: AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9517-4
If DLD is used, it is possible for the DLD signal to chatter some
while the PLL is reacquiring lock. The holdover function may
retrigger, thereby preventing the holdover mode from
terminating. Use of the current source lock detect mode is
recommended to avoid this situation (see the Current Source
Digital Lock Detect section).
Once in holdover mode, the charge pump stays in a high
impedance state as long as there is no reference clock present.
As in the external holdover mode, the B counter (in the N
divider) is reset synchronously with the charge pump leaving
the high impedance state on the reference path PFD event. This
helps align the edges out of the R and N dividers for faster
settling of the PLL and to reduce frequency errors during
settling. Because the prescaler is not reset, this feature works
best when the B and R numbers are close because this results in
a smaller phase difference for the loop to settle out.
After leaving holdover, the loop then reacquires lock and the
LD pin must charge (if Register 0x01D[3] = 1) before it can
re-enter holdover (CP high impedance).
The holdover function always responds to the state of the
currently selected reference (Register 0x01C). If the loop loses
lock during a reference switchover (see the Reference Switchover
section), holdover is triggered briefly until the next reference
clock edge at the PFD.
The following registers affect the internal/automatic holdover
function:
•
•
•
•
•
•
Register 0x018[6:5]. Lock detect counter. This changes how
many consecutive PFD cycles with edges inside the lock detect
window are required for the DLD indicator to indicate lock.
This impacts the time required before the LD pin can begin
to charge as well as the delay from the end of a holdover event
until the holdover function can be re-engaged.
Register 0x018[3]. Disable digital lock detect. This bit must
be set to a 0 to enable the DLD circuit. Internal/automatic
holdover does not operate correctly without the DLD function
enabled.
Register 0x01A[5:0]. Lock detect pin output select. Set this
to 000100b to put it in the current source lock detect mode
if using the LD pin comparator. Load the LD pin with a
capacitor of an appropriate value.
Register 0x01D[3]. Enable LD pin comparator; 1 = enable;
0 = disable. When disabled, the holdover function always
senses the LD pin as high.
Register 0x01D[1]. Enable external holdover control.
Register 0x01D[0] and Register 0x01D[2]. Holdover
function enable. If holdover is disabled, both external
and internal/automatic holdover are disabled.
Rev. B | Page 38 of 80
For example, to use automatic holdover with the following:
•
•
•
Set the following registers (in addition to the normal PLL registers):
•
•
•
•
•
•
•
•
•
•
•
Frequency Status Monitors
The AD9517 contains three frequency status monitors that are
used to indicate if the PLL reference (or references in the case of
single-ended mode) and the VCO have fallen below a threshold
frequency. A diagram showing their location in the PLL is shown
in Figure 53.
The PLL reference monitors have two threshold frequencies:
normal and extended (see Table 16). The reference frequency
monitor thresholds are selected in Register 0x01F.
Automatic reference switchover, prefer REF1
Digital lock detect: five PFD cycles, high range window
Automatic holdover using the LD pin comparator
Register 0x018[6:5] = 00b; lock detect counter = five cycles.
Register 0x018[4] = 0b; lock detect window = high range.
Register 0x018[3] = 0b; DLD normal operation.
Register 0x01A[5:0] = 000100b; current source lock detect
mode.
Register 0x01C[4] = 1b; automatic reference switchover
enabled.
Register 0x01C[3] = 0b; prefer REF1.
Register 0x01C[2:1] = 11b; enable REF1 and REF2 input
buffers.
Register 0x01D[3] = 1b; enable LD pin comparator.
Register 0x01D[2]=1b; enable the holdover function.
Register 0x01D[1] = 0b; use internal/automatic holdover
mode.
Register 0x01D[0] = 1b; enable the holdover function.