AD9517-4BCPZ Analog Devices Inc, AD9517-4BCPZ Datasheet - Page 76

• Manufacturer Part Number: AD9517-4BCPZ
• Description: IC CLOCK GEN 1.8GHZ VCO 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-4BCPZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.8GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 1.8GHz
• No. Of Outputs: 12
• Supply Current: 100µA
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Rohs Compliant: Yes
• For Use With: AD9517-4/PCBZ - BOARD EVALUATION AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9517-4
LVPECL CLOCK DISTRIBUTION
The LVPECL outputs of the AD9517 provide the lowest jitter
clock signals that are available from the AD9517. The LVPECL
outputs (because they are open emitter) require a dc termination
to bias the output transistors. The simplified equivalent circuit in
Figure 58 shows the LVPECL output stage.
In most applications, a LVPECL far-end Thevenin termination
(see Figure 70) or Y-termination (see Figure 71) is recommended.
In each case, the V
VS_LVPECL. If it does not, ac coupling is recommended (see
Figure 72).
VS_LVPECL
Figure 70. DC-Coupled 3.3 V LVPECL Far-End Thevenin Termination
Figure 72. AC-Coupled LVPECL with Parallel Transmission Line
VS_LVPECL
VS_LVPECL
LVPECL
LVPECL
LVPECL
Figure 71. DC-Coupled 3.3 V LVPECL Y-Termination
200Ω
S
0.1nF
0.1nF
(NOT COUPLED)
of the receiving buffer should match the
200Ω
SINGLE-ENDED
Z
Z
0
0
TRANSMISSION LINE
100Ω DIFFERENTIAL
50Ω
50Ω
= 50Ω
= 50Ω
(COUPLED)
127Ω
83Ω
VS_DRV
50Ω
100Ω
50Ω
50Ω
127Ω
83Ω
V
S
LVPECL
LVPECL
= 3.3V
V
S
LVPECL
V
S
Rev. B | Page 76 of 80
LVPECL Y-termination is an elegant termination scheme that
uses the fewest components and offers both odd- and even-mode
impedance matching. Even-mode impedance matching is an
important consideration for closely coupled transmission lines
at high frequencies. Its main drawback is that it offers limited
flexibility for varying the drive strength of the emitter-follower
LVPECL driver. This can be an important consideration when
driving long trace lengths but is usually not an issue. In the case
shown in Figure 71, where VS_LVPECL = 2.5 V, the 50 Ω
termination resistor that is connected to ground should be
changed to 19 Ω.
Thevenin-equivalent termination uses a resistor network to
provide 50 Ω termination to a dc voltage that is below V
the LVPECL driver. In this case, VS_LVPECL on the AD9517
should equal V
combination shown in Figure 71 results in a dc bias point of
VS_LVPECL − 2 V, the actual common-mode voltage is
VS_LVPECL − 1.3 V because additional current flows from the
AD9517 LVPECL driver through the pull-down resistor.
The circuit is identical when VS_LVPECL = 2.5 V, except that the
pull-down resistor is 62.5 Ω and the pull-up is 250 Ω.
LVDS CLOCK DISTRIBUTION
The AD9517 provides four clock outputs (OUT4 to OUT7) that
are selectable as either CMOS or LVDS level outputs. LVDS is a
differential output option that uses a current mode output stage.
The nominal current is 3.5 mA, which yields 350 mV output swing
across a 100 Ω resistor. An output current of 7 mA is also available
in cases where a larger output swing is required. The LVDS
output meets or exceeds all ANSI/TIA/EIA-644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 73.
See the AN-586 application note at www.analog.com for more
information on LVDS.
LVDS
V
S
S
of the receiving buffer. Although the resistor
Figure 73. LVDS Output Termination
DIFFERENTIAL (COUPLED)
100Ω
100Ω
LVDS
V
S
OL
of