AD9517-4BCPZ Analog Devices Inc, AD9517-4BCPZ Datasheet - Page 3

• Manufacturer Part Number: AD9517-4BCPZ
• Description: IC CLOCK GEN 1.8GHZ VCO 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-4BCPZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.8GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 1.8GHz
• No. Of Outputs: 12
• Supply Current: 100µA
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Rohs Compliant: Yes
• For Use With: AD9517-4/PCBZ - BOARD EVALUATION AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REVISION HISTORY
5/10—Rev. A to Rev. B
Changes to Default Values of LVDS/CMOS Outputs
Section in Table 52 .......................................................................... 56
Changes to Register 0x140, Bit 0; Register 0x142, Bit 0;
Register 0x143, Bit 0 in Table 57 ................................................... 69
Updated Outline Dimensions, Changes to Ordering Guide ..... 78
1/10—Rev. 0 to Rev. A
Added 48-Lead LFCSP Package (CP-48-8) .................... Universal
Changes to Features, Applications, and General Description ..... 1
Change to CPRSET Pin Resistor Parameter .................................. 4
Changes to Table 4 ............................................................................ 6
Changes to V
Changes to Table 19 ........................................................................ 16
Added Exposed Paddle Notation to Figure 6; Changes to
Table 20 ............................................................................................. 17
Change to High Frequency Clock Distribution—CLK or
External VCO > 1600 MHz Section; Change to Table 22 .......... 27
Changes to Table 24 ........................................................................ 29
Change to Configuration and Register Settings Section ............ 31
Change to Phase Frequency Detector (PFD) Section ................ 32
Changes to Charge Pump (CP), On-Chip VCO, PLL
External Loop Filter, and PLL Reference Inputs Sections ......... 33
Change to Figure 46; Added Figure 47 ......................................... 33
Changes to Reference Switchover and VCXO/VCO
Feedback Divider N—P, A, B, R Sections .................................... 34
Changes to Table 28 ........................................................................ 35
CP
Supply Parameter ................................................. 14
Rev. B | Page 3 of 80
Change to Holdover Section .......................................................... 37
Changes to VCO Calibration Section ........................................... 39
Changes to Clock Distribution Section ........................................ 40
Change to Clock Frequency Division Section;
Change to Table 34 .......................................................................... 41
Changes to Channel Dividers—LVDS/CMOS Outputs
Section; Change to Table 39 ........................................................... 43
Change to Write Section ................................................................ 50
Change to MSB/LSB First Transfers ............................................. 51
Change to Figure 64 ........................................................................ 52
Added Thermal Performance Section .......................................... 54
Changes to 0x003 Register Address .............................................. 55
Changes to Table 53 ........................................................................ 58
Changes to Table 54 ........................................................................ 59
Changes to Table 55 ........................................................................ 65
Changes to Table 56 ........................................................................ 67
Changes to Table 57 ........................................................................ 69
Changes to Table 58 ........................................................................ 71
Changes to Table 59 ........................................................................ 72
Changes to Table 60 and Table 61 ................................................. 74
Added Frequency Planning Using the AD9517 Section ............ 75
Changes to Figure 70 and Figure 72; Added Figure 71 .............. 76
Changes to LVDS Clock Distribution Section ............................ 76
Added Exposed Paddle Notation to Outline Dimensions ......... 78
Changes to Ordering Guide ........................................................... 78
7/07—Revision 0: Initial Version
AD9517-4