AD9517-4BCPZ Analog Devices Inc, AD9517-4BCPZ Datasheet - Page 59

• Manufacturer Part Number: AD9517-4BCPZ
• Description: IC CLOCK GEN 1.8GHZ VCO 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-4BCPZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.8GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 1.8GHz
• No. Of Outputs: 12
• Supply Current: 100µA
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Rohs Compliant: Yes
• For Use With: AD9517-4/PCBZ - BOARD EVALUATION AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 54. PLL
Reg.
Addr.
(Hex)
0x010
0x011
0x012
0x013
0x014
0x015
0x016
Bits
7
[6:4]
[3:2]
[1:0]
[7:0]
[5:0]
[5:0]
[7:0]
[4:0]
7
6
5
4
3
Name
PFD polarity
CP current
CP mode
PLL power-
down
14-bit R divider,
Bits[7:0] (LSB)
14-bit R divider,
Bits[13:8] (MSB)
6-bit A counter
13-bit B counter,
Bits[7:0] (LSB)
13-bit B counter,
Bits[12:8] (MSB)
Set CP pin to V
Reset R counter
Reset A, B counters
Reset all counters
B counter
bypass
CP
/2
Description
Sets the PFD polarity. Negative polarity is for use (if needed) with external VCO/VCXO only. The on-chip VCO requires
positive polarity; Bit 7 = 0.
0: positive; higher control voltage produces higher frequency (default).
1: negative; higher control voltage produces lower frequency.
Charge pump current (with CPRSET = 5.1 kΩ).
6
0
0
0
0
1
1
1
1
Charge pump operating mode.
3
0
0
1
1
PLL operating mode.
1
0
0
1
1
R divider LSBs—lower eight bits (default = 0x01).
R divider MSBs—upper six bits (default = 0x00).
A counter (part of N divider) (default = 0x00).
B counter (part of N divider)—lower eight bits (default = 0x03).
B counter (part of N divider)—upper five bits (default = 0x00).
Set the CP pin to one-half of the V
0: CP normal operation (default).
1: CP pin set to V
Reset R counter (R divider).
0: normal (default).
1: holds the R counter in reset.
Reset A and B counters (part of N divider).
0: normal (default).
1: holds the A and B counters in reset.
Reset R, A, and B counters.
0: normal (default).
1: holds the R, A, and B counters in reset.
B counter bypass. This is valid only when operating the prescaler in FD mode.
0: normal (default).
1: B counter is set to divide-by-1. This allows the prescaler setting to determine the divide for the N divider.
5
0
0
1
1
0
0
1
1
2
0
1
0
1
0
0
1
0
1
4
0
1
0
1
0
1
0
1
Charge Pump Mode
High impedance state.
Force source current (pump up).
Force sink current (pump down).
Normal operation (default).
Mode
Normal operation.
Asynchronous power-down (default).
Normal operation.
Synchronous power-down.
I
0.6
1.2
1.8
2.4
3.0
3.6
4.2
4.8 (default)
CP
CP
/2.
(mA)
Rev. B | Page 59 of 80
CP
supply voltage.
AD9517-4