AD9517-4BCPZ Analog Devices Inc, AD9517-4BCPZ Datasheet - Page 8

• Manufacturer Part Number: AD9517-4BCPZ
• Description: IC CLOCK GEN 1.8GHZ VCO 48-LFCSP
• Manufacturer: Analog Devices Inc
• Type: Clock Generator, Fanout Distributionr

Specifications of AD9517-4BCPZ

• Design Resources: High Performance, Dual Channel IF Sampling Receiver (CN0140)
• Pll: Yes
• Input: CMOS, LVDS, LVPECL
• Output: CMOS, LVDS, LVPECL
• Number Of Circuits: 1
• Ratio - Input:output: 1:12
• Differential - Input:output: Yes/Yes
• Frequency - Max: 1.8GHz
• Divider/multiplier: Yes/No
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LFCSP
• Frequency-max: 1.8GHz
• Clock Ic Type: Clock Generator
• Ic Interface Type: Serial
• Frequency: 1.8GHz
• No. Of Outputs: 12
• Supply Current: 100µA
• Supply Voltage Range: 3.135V To 3.465V
• Digital Ic Case Style: LFCSP
• Rohs Compliant: Yes
• For Use With: AD9517-4/PCBZ - BOARD EVALUATION AD9517-4
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD9517-4
CLOCK OUTPUT ADDITIVE PHASE NOISE (DISTRIBUTION ONLY; VCO DIVIDER NOT USED)
Table 6.
Parameter
CLK-TO-LVPECL ADDITIVE PHASE NOISE
CLK-TO-LVDS ADDITIVE PHASE NOISE
CLK-TO-CMOS ADDITIVE PHASE NOISE
CLK = 1 GHz, OUTPUT = 1 GHz
Divider = 1
CLK = 1 GHz, OUTPUT = 200 MHz
Divider = 5
CLK = 1.6 GHz, OUTPUT = 800 MHz
Divider = 2
CLK = 1.6 GHz, OUTPUT = 400 MHz
Divider = 4
CLK = 1 GHz, OUTPUT = 250 MHz
Divider = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
@ 10 MHz Offset
@ 100 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
@ 10 MHz Offset
@ 100 MHz Offset
>10 MHz Offset
Min
Typ
−109
−118
−130
−139
−144
−146
−147
−149
−120
−126
−139
−150
−155
−157
−157
−103
−110
−120
−127
−133
−138
−147
−149
−114
−122
−132
−140
−146
−150
−155
−110
−120
−127
−136
−144
−147
−154
Rev. B | Page 8 of 80
Max
Unit
dBc/Hz
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Test Conditions/Comments
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns
Input slew rate > 1 V/ns
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns
Input slew rate > 1 V/ns
Distribution section only; does not include PLL and VCO
Input slew rate > 1 V/ns